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Thu, 21 May 2026 15:52:56 +0000 (GMT) Received: from [9.39.16.234] (unknown [9.39.16.234]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 21 May 2026 15:52:56 +0000 (GMT) Message-ID: Date: Thu, 21 May 2026 21:22:54 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [patch V6 05/16] x86/irq: Suppress unlikely interrupt stats by default To: Thomas Gleixner , LKML Cc: x86@kernel.org, Michael Kelley , Dmitry Ilvokhin , Radu Rendec , Jan Kiszka , Kieran Bingham , Florian Fainelli , Marc Zyngier References: <20260517194421.705253664@kernel.org> <20260517194931.276486277@kernel.org> Content-Language: en-US From: Shrikanth Hegde In-Reply-To: <20260517194931.276486277@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-ORIG-GUID: CMIwWsHvBKANjFXU2V8agVAfFMOqIAqS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIxMDE1NyBTYWx0ZWRfX5kG1Rerk9a6k f+KYui6sxuO0qQCFUZDVQIFc7znzAHjtXAxhrJBOufoC4On67hPHBYUjF5x90vE0NXnZKR59zr2 351OK7eU+SaEJcFo2umnBR8LWRdqPhmOqvZSCDlVSQARX9Vrpam9hbsfEUUmnxwVTV01CMTXZHM WG8BxZ6dRFEswBu5ycqjX1l88bkvsiOqqbtljGkOYn7D3JgTCURJcdSC3V52sV48Oj7GVfdKrB8 gM4DhECO1/Td2D9w25lp8OPZqX8FQ1ILQLRAMZGK7oEHaWoid59q7DPg3+x8Map4orB/DlTNvie hG0rWnyTBZO4V9rqirlrtRfBjxwTOGTKtcOUuEAj3MQi0M0Atrj60LSdJBnKf6xX0RjIoMFAlxT Hl7orWjVTVSdi/0QMhZYo/Sw32hZ9ESewV2eF/V+vNZ0vACGL+ZviGsuEWKE7oHuSdASp4sNgmJ GDQCxi/2TEb+1q3waIA== X-Proofpoint-GUID: xp6nGPWd-XpT4CqQMRSpFLcWcukC3oYT X-Authority-Analysis: v=2.4 cv=apyCzyZV c=1 sm=1 tr=0 ts=6a0f2a60 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=VwQbUJbxAAAA:8 a=UqCG9HQmAAAA:8 a=coPjFYPWAAAA:8 a=57NzquixjKAFE_L30ysA:9 a=QEXdDO2ut3YA:10 a=PHqHxvoSLtS9In37M5wo:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-21_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 suspectscore=0 adultscore=0 spamscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605210157 On 5/18/26 1:31 AM, Thomas Gleixner wrote: > From: Thomas Gleixner > > Unlikely interrupt counters like the spurious vector and the synthetic APIC > ICR read retry show up in /proc/interrupts with all counts 0 most of the > time. > > As these are events which should never happen, suppress them by default and > enable them for output when they actually happen. > > This requires a seperate bitmap as the description array is marked > __ro_after_init. With that bitmap in place it becomes RO data. > > Signed-off-by: Thomas Gleixner > Tested-by: Michael Kelley > Reviewed-by: Radu Rendec > --- > V5: Move irq_stat_inc_and_enable() here > V4: Fix the bad idea of writing to __ro_after_init marked data > V3: New patch > --- > arch/x86/include/asm/hardirq.h | 1 + > arch/x86/kernel/apic/apic.c | 2 +- > arch/x86/kernel/apic/ipi.c | 2 +- > arch/x86/kernel/irq.c | 38 ++++++++++++++++++++++++++++---------- > 4 files changed, 31 insertions(+), 12 deletions(-) > --- a/arch/x86/include/asm/hardirq.h > +++ b/arch/x86/include/asm/hardirq.h > @@ -68,6 +68,7 @@ DECLARE_PER_CPU_ALIGNED(struct pi_desc, > #define __ARCH_IRQ_STAT > > #define inc_irq_stat(index) this_cpu_inc(irq_stat.counts[IRQ_COUNT_##index]) > +void irq_stat_inc_and_enable(enum irq_stat_counts which); > > #ifdef CONFIG_X86_LOCAL_APIC > #define inc_perf_irq_stat() inc_irq_stat(APIC_PERF) > --- a/arch/x86/kernel/apic/apic.c > +++ b/arch/x86/kernel/apic/apic.c > @@ -2114,7 +2114,7 @@ static noinline void handle_spurious_int > > trace_spurious_apic_entry(vector); > > - inc_irq_stat(SPURIOUS); > + irq_stat_inc_and_enable(IRQ_COUNT_SPURIOUS); > > /* > * If this is a spurious interrupt then do not acknowledge > --- a/arch/x86/kernel/apic/ipi.c > +++ b/arch/x86/kernel/apic/ipi.c > @@ -120,7 +120,7 @@ u32 apic_mem_wait_icr_idle_timeout(void) > for (cnt = 0; cnt < 1000; cnt++) { > if (!(apic_read(APIC_ICR) & APIC_ICR_BUSY)) > return 0; > - inc_irq_stat(ICR_READ_RETRY); > + irq_stat_inc_and_enable(IRQ_COUNT_ICR_READ_RETRY); > udelay(100); > } > return APIC_ICR_BUSY; > --- a/arch/x86/kernel/irq.c > +++ b/arch/x86/kernel/irq.c > @@ -68,19 +68,24 @@ struct irq_stat_info { > const char *text; > }; > > +#define DEFAULT_SUPPRESSED_VECTOR UINT_MAX > + > #define ISS(idx, sym, txt) [IRQ_COUNT_##idx] = { .symbol = sym, .text = txt } > > #define ITS(idx, sym, txt) [IRQ_COUNT_##idx] = \ > { .skip_vector = idx## _VECTOR, .symbol = sym, .text = txt } > > -static struct irq_stat_info irq_stat_info[IRQ_COUNT_MAX] __ro_after_init = { > +#define IDS(idx, sym, txt) [IRQ_COUNT_##idx] = \ > + { .skip_vector = DEFAULT_SUPPRESSED_VECTOR, .symbol = sym, .text = txt } > + > +static const struct irq_stat_info irq_stat_info[IRQ_COUNT_MAX] = { > ISS(NMI, "NMI", " Non-maskable interrupts\n"), > #ifdef CONFIG_X86_LOCAL_APIC > ISS(APIC_TIMER, "LOC", " Local timer interrupts\n"), > - ISS(SPURIOUS, "SPU", " Spurious interrupts\n"), > + IDS(SPURIOUS, "SPU", " Spurious interrupts\n"), > ISS(APIC_PERF, "PMI", " Performance monitoring interrupts\n"), > ISS(IRQ_WORK, "IWI", " IRQ work interrupts\n"), > - ISS(ICR_READ_RETRY, "RTR", " APIC ICR read retries\n"), > + IDS(ICR_READ_RETRY, "RTR", " APIC ICR read retries\n"), > ISS(X86_PLATFORM_IPI, "PLT", " Platform interrupts\n"), > #endif > #ifdef CONFIG_SMP > @@ -121,34 +126,47 @@ static struct irq_stat_info irq_stat_inf > #endif > }; > > +static DECLARE_BITMAP(irq_stat_count_show, IRQ_COUNT_MAX) __read_mostly; > + > static int __init irq_init_stats(void) > { > - struct irq_stat_info *info = irq_stat_info; > + const struct irq_stat_info *info = irq_stat_info; > > for (unsigned int i = 0; i < ARRAY_SIZE(irq_stat_info); i++, info++) { > - if (info->skip_vector && test_bit(info->skip_vector, system_vectors)) > - info->skip_vector = 0; > + if (!info->skip_vector || (info->skip_vector != DEFAULT_SUPPRESSED_VECTOR && > + test_bit(info->skip_vector, system_vectors))) > + set_bit(i, irq_stat_count_show); > } > > #ifdef CONFIG_X86_LOCAL_APIC > if (!x86_platform_ipi_callback) > - irq_stat_info[IRQ_COUNT_X86_PLATFORM_IPI].skip_vector = 1; > + clear_bit(IRQ_COUNT_X86_PLATFORM_IPI, irq_stat_count_show); > #endif > > #ifdef CONFIG_X86_POSTED_MSI > if (!posted_msi_enabled()) > - irq_stat_info[IRQ_COUNT_POSTED_MSI_NOTIFICATION].skip_vector = 1; > + clear_bit(IRQ_COUNT_POSTED_MSI_NOTIFICATION, irq_stat_count_show); > #endif > > #ifdef CONFIG_X86_MCE_AMD > if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD && > boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) > - irq_stat_info[IRQ_COUNT_DEFERRED_ERROR].skip_vector = 1; > + clear_bit(IRQ_COUNT_DEFERRED_ERROR, irq_stat_count_show); > #endif > return 0; > } > late_initcall(irq_init_stats); > > +/* > + * Used for default enabled counters to increment the stats and to enable the > + * entry for /proc/interrupts output. > + */ > +void irq_stat_inc_and_enable(enum irq_stat_counts which) > +{ > + this_cpu_inc(irq_stat.counts[which]); > + set_bit(which, irq_stat_count_show); > +} > + > #ifdef CONFIG_PROC_FS > /* > * /proc/interrupts printing for arch specific interrupts > @@ -158,7 +176,7 @@ int arch_show_interrupts(struct seq_file > const struct irq_stat_info *info = irq_stat_info; > > for (unsigned int i = 0; i < ARRAY_SIZE(irq_stat_info); i++, info++) { > - if (info->skip_vector) > + if (!test_bit(i, irq_stat_count_show)) > continue; If this is done, then those lines will be absent in /proc/interrupts right? If there was a tool expecting these entries, it will fail get to see that entry. Is that ok? > > seq_printf(p, "%*s:", prec, info->symbol); >