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([2a01:e0a:3d9:2080:3e43:d171:89d1:18e8]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c3abf0csm45909628f8f.14.2025.08.13.01.26.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Aug 2025 01:26:20 -0700 (PDT) Message-ID: Date: Wed, 13 Aug 2025 10:26:19 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: Neil Armstrong Subject: Re: [PATCH v2] media: iris: vpu3x: Add MNoC low power handshake during hardware power-off To: Dikshita Agarwal , Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250813-sm8650-power-sequence-fix-v2-1-9ed0fc2c45cb@quicinc.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20250813-sm8650-power-sequence-fix-v2-1-9ed0fc2c45cb@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 13/08/2025 09:53, Dikshita Agarwal wrote: > Add the missing write to AON_WRAPPER_MVP_NOC_LPI_CONTROL before > reading the LPI status register. Introduce a handshake loop to ensure > MNoC enters low power mode reliably during VPU3 hardware power-off with > timeout handling. > > Signed-off-by: Dikshita Agarwal > --- > Changes in v2: > - Restructured loop for readability (Jorge) > - Used defines for bits (Konrad, Jorge) > - Used udelay for short waits (Konrad) > - Link to v1: https://lore.kernel.org/r/20250812-sm8650-power-sequence-fix-v1-1-a51e7f99c56c@quicinc.com > > Please note that I have not added "Tested-by" tag from Neil in this update, > as the NOC handshake loop has been restructured. > --- > drivers/media/platform/qcom/iris/iris_vpu3x.c | 30 +++++++++++++++++++++++++-- > 1 file changed, 28 insertions(+), 2 deletions(-) > > diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c > index 9b7c9a1495ee2f51c60b1142b2ed4680ff798f0a..a621878f02f7196de29c9e290a6c5acea34eba8c 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c > +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c > @@ -19,6 +19,9 @@ > #define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) > #define REQ_POWER_DOWN_PREP BIT(0) > #define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) > +#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */ > +#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */ > +#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ > #define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) > #define CORE_CLK_RUN 0x0 > > @@ -109,7 +112,9 @@ static void iris_vpu3_power_off_hardware(struct iris_core *core) > > static void iris_vpu33_power_off_hardware(struct iris_core *core) > { > + bool handshake_done = false, handshake_busy = false; > u32 reg_val = 0, value, i; > + u32 count = 0; > int ret; > > if (iris_vpu3x_hw_power_collapsed(core)) > @@ -128,13 +133,34 @@ static void iris_vpu33_power_off_hardware(struct iris_core *core) > goto disable_power; > } > > + /* set MNoC to low power */ > + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); > + > + do { > + value = readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS); > + > + handshake_done = value & NOC_LPI_STATUS_DONE; > + handshake_busy = value & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE); > + > + if (handshake_done || !handshake_busy) > + break; > + > + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); > + > + udelay(15); > + > + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); > + } while (++count < 1000); > + > + if (!handshake_done && handshake_busy) > + dev_err(core->dev, "LPI handshake timeout\n"); > + > ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS, > reg_val, reg_val & BIT(0), 200, 2000); > if (ret) > goto disable_power; > > - /* set MNoC to low power, set PD_NOC_QREQ (bit 0) */ > - writel(BIT(0), core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); > + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); > > writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, > core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); > > --- > base-commit: d968e50b5c26642754492dea23cbd3592bde62d8 > change-id: 20250812-sm8650-power-sequence-fix-ba9a92098233 > > Best regards, Tested-by: Neil Armstrong # on SM8650-QRD Tested-by: Neil Armstrong # on SM8650-HDK Thanks, Neil