From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 545B4C433F5 for ; Mon, 28 Mar 2022 01:30:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237278AbiC1Bbw (ORCPT ); Sun, 27 Mar 2022 21:31:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237266AbiC1Bbu (ORCPT ); Sun, 27 Mar 2022 21:31:50 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7EFC192A3; Sun, 27 Mar 2022 18:30:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648431010; x=1679967010; h=message-id:subject:from:to:cc:date:in-reply-to: references:mime-version:content-transfer-encoding; bh=beeEYxcAp4r2iI1wWi4YsTfFuc4wGRqsztjNxGViHVo=; b=XO8g38G2bWH4+JnyjpMH6hxOntFrTFxmN/dc2izRzl2LkLfjpUWGS2r+ a2X27CFZf7WAhfKbrRLiCTkJMdu6d8WR0eO6ztj9uekGE/z7QIkp8heqd OXKC0WgCnwMLxCiWOibsaDvwnfU6kz+CyiCZa+b1oeB4kAo14QJFyq+bs MJ3YFx/3WS6/PYFjaZwbCKlTdT4Kg0RDTKwrTF2ZqxVR2AmEZCkiyoGt4 2xhhVuk+2xuy/2B5v1V63L1AlqRiIWwpXSPVqOXuMe9/ZEbeMaiQGNiO/ jko2p/F6lfPfS6TW1sSzbzP6Lrif7up/PQahfQ9TUtx/Gmtuthq4Ei2jH Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10299"; a="257718836" X-IronPort-AV: E=Sophos;i="5.90,216,1643702400"; d="scan'208";a="257718836" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Mar 2022 18:30:10 -0700 X-IronPort-AV: E=Sophos;i="5.90,216,1643702400"; d="scan'208";a="585016682" Received: from stung2-mobl.gar.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.255.94.73]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Mar 2022 18:30:07 -0700 Message-ID: Subject: Re: [PATCH v2 09/21] x86/virt/tdx: Get information about TDX module and convertible memory From: Kai Huang To: Isaku Yamahata Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, dave.hansen@intel.com, seanjc@google.com, pbonzini@redhat.com, kirill.shutemov@linux.intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, peterz@infradead.org, tony.luck@intel.com, ak@linux.intel.com, dan.j.williams@intel.com, isaku.yamahata@intel.com Date: Mon, 28 Mar 2022 14:30:05 +1300 In-Reply-To: <20220324174301.GA1212881@ls.amr.corp.intel.com> References: <98c1010509aa412e7f05b12187cacf40451d5246.1647167475.git.kai.huang@intel.com> <20220324174301.GA1212881@ls.amr.corp.intel.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.42.4 (3.42.4-1.fc35) MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > + > > +static int sanitize_cmrs(struct cmr_info *cmr_array, int cmr_num) > > +{ > > + int i, j; > > + > > + /* > > + * Intel TDX module spec, 20.7.3 CMR_INFO: > > + * > > + * TDH.SYS.INFO leaf function returns a MAX_CMRS (32) entry > > + * array of CMR_INFO entries. The CMRs are sorted from the > > + * lowest base address to the highest base address, and they > > + * are non-overlapping. > > + * > > + * This implies that BIOS may generate invalid empty entries > > + * if total CMRs are less than 32. Skip them manually. > > + */ > > + for (i = 0; i < cmr_num; i++) { > > + struct cmr_info *cmr = &cmr_array[i]; > > + struct cmr_info *prev_cmr = NULL; > > + > > + /* Skip further invalid CMRs */ > > + if (!cmr_valid(cmr)) > > + break; > > + > > + if (i > 0) > > + prev_cmr = &cmr_array[i - 1]; > > + > > + /* > > + * It is a TDX firmware bug if CMRs are not > > + * in address ascending order. > > + */ > > + if (prev_cmr && ((prev_cmr->base + prev_cmr->size) > > > + cmr->base)) { > > + pr_err("Firmware bug: CMRs not in address ascending order.\n"); > > + return -EFAULT; > > + } > > + } > > + > > + /* > > + * Also a sane BIOS should never generate invalid CMR(s) between > > + * two valid CMRs. Sanity check this and simply return error in > > + * this case. > > + */ > > + for (j = i; j < cmr_num; j++) > > + if (cmr_valid(&cmr_array[j])) { > > + pr_err("Firmware bug: invalid CMR(s) among valid CMRs.\n"); > > + return -EFAULT; > > + } > > This check doesn't make sense because above i-for loop has break. The break in above i-for loop will hit at the first invalid CMR entry. Yes "j = i" will make double check on this invalid CMR entry, but it should have no problem. Or we can change to "j = i + 1" to skip the first invalid CMR entry. Does this make sense? > > > + > > + /* > > + * Trim all tail invalid empty CMRs. BIOS should generate at > > + * least one valid CMR, otherwise it's a TDX firmware bug. > > + */ > > + tdx_cmr_num = i; > > + if (!tdx_cmr_num) { > > + pr_err("Firmware bug: No valid CMR.\n"); > > + return -EFAULT; > > + } > > Something strange. > Probably we'd like to check it by decrementing. > for (i = cmr_num; i >= 0; i--) > if (!cmr_valid()) // if last invalid cmr > tdx_cmr_num > // more check. overlapping > I don't know how does this look strange to you? As replied above, "i" is the index to the first invalid CMR entry (or cmr_num, which is array size), so "tdx_cmr_num = i" initializes the total valid CMR number, correct?