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On 19/06/26 23:03, Mark Brown wrote: > On Thu, Jun 18, 2026 at 01:07:17PM +0530, Santhosh Kumar K wrote: >> The Cadence QSPI controller supports a delay-line PHY for high-speed >> operation. Without calibration the PHY is unused and read capture relies >> on a fixed delay, limiting throughput at frequencies above the base >> operating speed. > >> +static int cqspi_get_phy_pattern_offset(struct device *dev, u32 *offset) >> +{ >> + struct device_node *np, *flash_np = NULL, *part_np; >> + const __be32 *reg; >> + int len; >> + >> + if (!dev || !dev->of_node) >> + return -EINVAL; >> + >> + for_each_child_of_node(dev->of_node, np) { >> + if (of_node_name_prefix(np, "flash")) { >> + flash_np = np; >> + break; >> + } >> + } > > This isn't going to do the right thing if there's more than one flash, > that doesn't seem a super sensible hardware configuration but I'm not > sure I see anything stopping it being set up and system integrators do > enjoy differentiating. Oops, I missed this while testing with only a single flash connected. Thanks for catching it, I'll update the driver to store the offset during cqspi_of_get_flash_pdata(), which should resolve the issue. Thanks, Santhosh.