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Peter Anvin" , Andrew Morton , Jann Horn , kasan-dev@googlegroups.com Subject: Re: [PATCH] x86/kfence: Avoid writing L1TF-vulnerable PTEs To: Alexander Potapenko References: <20260106180426.710013-1-andrew.cooper3@citrix.com> Content-Language: en-GB From: Andrew Cooper In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: LO0P265CA0006.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:355::17) To IA1PR03MB8288.namprd03.prod.outlook.com (2603:10b6:208:59e::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH8PR03MB8275:EE_|BN8PR03MB5090:EE_ X-MS-Office365-Filtering-Correlation-Id: 54b709b4-0683-424b-5cb8-08de4de49185 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|7416014|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?L3MvNzliSlcvU3cyZk9qOGJLbGRyMWVRRDJjaGhvZG9lYXEyR0hKVWhSQ2tR?= =?utf-8?B?T1ZLUzJydzNXdDVhVUpEYVhSVlRwd3BCNWdNT2E2a2JZM0piQUJsdnZId1dY?= =?utf-8?B?UjEzV1FDTFVWL2F4dG5kT3RPNThZaW9oRC9xeCtUWFZlZkFzMGVYNmxiTzJW?= =?utf-8?B?cSt4OGtrZDBVejFucys4M3NvY3ZqRk9uelFCbmljRHF3WDNjMUlRVUhXMDgx?= =?utf-8?B?RXZYMVhvaVdFRGtUck05TEJadWorNDdUQlBsMzV0NGdDZkRNeUZLZXdRK3hN?= =?utf-8?B?KzhRa3NNL2FkWHhYWlNqNmkwODVtMWtzS3pwdjBZd21Tb3paN2VLWC83S1p1?= =?utf-8?B?N3liV1hHYVF2MGhXQ096MDVsNldoMnJ0MnBoUkpzSkc3T3BxKy9ZRStZellO?= =?utf-8?B?RGMzNnNGcTlFQkhnY0lDTlJOekNPWGkrQmtMVXRSK0pBM0l5QXNnUjMrWDZl?= =?utf-8?B?Q3dNT3RqTVVNU09aLzNkZm9vTkR2cEF5S1Ayak9yWXl5M3ZZOStEb01yV0VD?= =?utf-8?B?b1JoMFl3TzNqL3piaitKM3VtLy9IV0pHTTNRaWZqOHpEWnU3UlRQS3pPb0xX?= =?utf-8?B?T3ZPVjVMMXoyT2lpZTB1WkVwUEM4QlFuamhybVh4WDlXWVRVam8raURvRjNh?= =?utf-8?B?c1pHWXZ5ME1QK1A0TzhRbUhmQ1RVaXJHblRobDMzaFBOdmxPT09WMDBTbEZk?= =?utf-8?B?aDNwMU9pOXA4MmpSRjBxdHFsK2pQb1pGTXAxa1AvUzRGTzY4bmEzNENCaE5X?= =?utf-8?B?Tzgxc3NIY3E5Tm9UMEhPWHpvMzN0VXk0SDVEUWVMbnFMeUpFODZ0bE1McU9X?= =?utf-8?B?VWkraG5uS1pPM05jZTVjcVpjTFpRcDFqb0xvcEh4SFppaG5Oakk0Z1djZGti?= =?utf-8?B?MGRsbldoWlJMK0o4c2Jydk5BR1RqeXZIcmJJUmVuenFTdmdHSU1BaGxpK0VL?= =?utf-8?B?bVZ3eWlsSXNTZEJBN25tUmZseVIwbEwyUEZoc2dkRUpUdWJrMU9RUG44dUhX?= =?utf-8?B?OGtLT041V2Qxby9oRkFsc09MSWdFWFpDQ1o4dmZtL2xNYjdwT0dlT0RMQjMy?= =?utf-8?B?eFQwcFRYV010UmJXUWdMMGN0NzRxZ2NrbC8yalZLYmFqY3JQUGVIOGNjOU5w?= =?utf-8?B?OStYckdGNktWZ2VPNk9hUzAzZXdOS1F2L29HRW1rZks4N2lKbi9BSVM3QzVI?= =?utf-8?B?UjdiZ0pnUmJjMmFiVkxmRjJpMXk0Z3VZNktlSlRCejA3TFpzaklud3Z6bUlJ?= =?utf-8?B?MVNMTFdTalh3OEtHNVNVa0JqRUZpQjRERFNDbDAwQkFYd1ZSVVR6NWpQczBM?= =?utf-8?B?aGR3L1pJckN2Rmh0MnZ0aWRQWWVxZ3lNR1V1b1cySTVMQ1pCM1ZsNkhHU2NO?= =?utf-8?B?WGs3YXJvZEJmZTVEc2lFZFZqWW84VFhCQUV6bG5OdFFlSTlsTWUzZ0U0YVk1?= =?utf-8?B?RVhUeCtWREZ1V3liRHJCUkI5RFVtN092SzdJQXV4eTM0QXpvcnB4WXd6UTBP?= =?utf-8?B?VGVQY0lWM0plUzFCVjV4SG1vRkZlWEdDSzVIZll1Z3c4WGREVmNxUjhiTUE0?= =?utf-8?B?a24zV09wRGRjak8vU3lLYytKeTUrNG8rdVhsb2s5eFpuSTJUSlhRZ04xTU1t?= =?utf-8?B?cS9NNG1GMm5mWUg1SWk0R1ZmV0pOY2MydVR2ck1QUktnZDR1L1o2czdTZW1m?= =?utf-8?B?TW91c1dnRDM2akRHM2N2VUJqWENxS3MwWDVSdUw1NkhCaUFQajQrd0I4WWpk?= =?utf-8?B?VEdSSlk4V1NEdS9NcHZTUUdzQi96SUJJSXpTRy9jb3dhN3IvazNmV1F0RTc3?= =?utf-8?B?QlRoakNGc0ZnOFdncWZSVXZYSHU0WlN2bVdLZWhNVDRvTU03bzNGWEhGTGJY?= =?utf-8?B?WEsybVM5MDcvYzM0OUJOeldGd1pQT0tKYUtSRTFLSlNHdDd0N1gxN2hkdWR4?= =?utf-8?Q?Y5f68BxzcwB6O+puWAbRLcJgbIYHh7qT?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH8PR03MB8275.namprd03.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(7416014)(376014);DIR:OUT;SFP:1101; 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There's real memory backing the >> non-present PTE. However, for XenPV, Xen complains: >> >> (XEN) d1 L1TF-vulnerable L1e 8010000018200066 - Shadowing >> >> To explain, some background on XenPV pagetables: >> >> Xen PV guests are control their own pagetables; they choose the new PTE >> value, and use hypercalls to make changes so Xen can audit for safety. >> >> In addition to a regular reference count, Xen also maintains a type >> reference count. e.g. SegDesc (referenced by vGDT/vLDT), >> Writable (referenced with _PAGE_RW) or L{1..4} (referenced by vCR3 or a >> lower pagetable level). This is in order to prevent e.g. a page being >> inserted into the pagetables for which the guest has a writable mapping. >> >> For non-present mappings, all other bits become software accessible, and >> typically contain metadata rather a real frame address. There is nothing >> that a reference count could sensibly be tied to. As such, even if Xen >> could recognise the address as currently safe, nothing would prevent that >> frame from changing owner to another VM in the future. >> >> When Xen detects a PV guest writing a L1TF-PTE, it responds by activating >> shadow paging. This is normally only used for the live phase of >> migration, and comes with a reasonable overhead. >> >> KFENCE only cares about getting #PF to catch wild accesses; it doesn't care >> about the value for non-present mappings. Use a fully inverted PTE, to >> avoid hitting the slow path when running under Xen. >> >> While adjusting the logic, take the opportunity to skip all actions if the >> PTE is already in the right state, half the number PVOps callouts, and skip >> TLB maintenance on a !P -> P transition which benefits non-Xen cases too. >> >> Fixes: 1dc0da6e9ec0 ("x86, kfence: enable KFENCE for x86") >> Tested-by: Marco Elver >> Signed-off-by: Andrew Cooper > Reviewed-by: Alexander Potapenko Thanks. > >> /* >> * We need to avoid IPIs, as we may get KFENCE allocations or faults >> * with interrupts disabled. Therefore, the below is best-effort, and >> @@ -53,11 +77,6 @@ static inline bool kfence_protect_page(unsigned long addr, bool protect) >> * lazy fault handling takes care of faults after the page is PRESENT. >> */ > Nit: should this comment be moved above before set_pte() or merged wit > the following comment block? Hmm, probably merged as they're both about the TLB maintenance.  But the end result is a far more messy diff: @@ -42,23 +42,40 @@ static inline bool kfence_protect_page(unsigned long addr, bool protect)  {         unsigned int level;         pte_t *pte = lookup_address(addr, &level); +       pteval_t val;           if (WARN_ON(!pte || level != PG_LEVEL_4K))                 return false;   +       val = pte_val(*pte); +         /* -        * We need to avoid IPIs, as we may get KFENCE allocations or faults -        * with interrupts disabled. Therefore, the below is best-effort, and -        * does not flush TLBs on all CPUs. We can tolerate some inaccuracy; -        * lazy fault handling takes care of faults after the page is PRESENT. +        * protect requires making the page not-present.  If the PTE is +        * already in the right state, there's nothing to do. +        */ +       if (protect != !!(val & _PAGE_PRESENT)) +               return true; + +       /* +        * Otherwise, invert the entire PTE.  This avoids writing out an +        * L1TF-vulnerable PTE (not present, without the high address bits +        * set).          */ +       set_pte(pte, __pte(~val));   -       if (protect) -               set_pte(pte, __pte(pte_val(*pte) & ~_PAGE_PRESENT)); -       else -               set_pte(pte, __pte(pte_val(*pte) | _PAGE_PRESENT)); +       /* +        * If the page was protected (non-present) and we're making it +        * present, there is no need to flush the TLB at all. +        */ +       if (!protect) +               return true;           /* +        * We need to avoid IPIs, as we may get KFENCE allocations or faults +        * with interrupts disabled. Therefore, the below is best-effort, and +        * does not flush TLBs on all CPUs. We can tolerate some inaccuracy; +        * lazy fault handling takes care of faults after the page is PRESENT. +        *          * Flush this CPU's TLB, assuming whoever did the allocation/free is          * likely to continue running on this CPU.          */ I need to resubmit anyway, because I've spotted one silly error in the commit message. I could submit two patches, with the second one stated as "to make the previous patch legible". Thoughts? ~Andrew