From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932164AbdJJHTe (ORCPT ); Tue, 10 Oct 2017 03:19:34 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:19720 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932143AbdJJHTc (ORCPT ); Tue, 10 Oct 2017 03:19:32 -0400 Subject: Re: [PATCH 1/2] PCI: dwc: dra7xx: Create functional dependency between PCIe and PHY To: Kishon Vijay Abraham I , Bjorn Helgaas CC: , , , References: <20171009090338.26033-1-kishon@ti.com> <20171009090338.26033-2-kishon@ti.com> From: Roger Quadros Message-ID: Date: Tue, 10 Oct 2017 10:19:28 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: <20171009090338.26033-2-kishon@ti.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-GB X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by nfs id v9A7JiQ2020965  Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki On 09/10/17 12:03, Kishon Vijay Abraham I wrote: > PCI core access configuration space registers in resume_noirq callbacks. > In the case of dra7xx, PIPE3 PHY connected to PCIe controller has to be > enabled before accessing configuration space registers. Since > PIPE3 PHY is enabled by only configuring control module registers, no > aborts has been observed so far (though during noirq stage, interface > clock of PIPE3 PHY is not enabled). > > With new TRM updates, PIPE3 PHY has to be initialized (PIPE3 PHY > registers has to be accessed) as well which requires the interface > clock of PIPE3 PHY to be enabled. The interface clock of PIPE3 PHY is > derived from OCP2SCP and hence PCIe PHY is modeled as a child of > OCP2SCP. Since pm_runtime is not enabled during noirq stage, > pm_runtime_get_sync done in phy_init doesn't enable > OCP2SCP clocks resulting in abort when PIPE3 PHY registers are > accessed. This could be the case not only with PCIe but even with USB and SATA? Maybe today it doesn't complain because USB/SATA is being resumed (by chance) after PHY? > > Create a function dependency between PCIe and PHY here to make > sure PCIe is suspended before PCIe PHY/OCP2SCP and resumed after > PCIe PHY/OCP2SCP. > > Suggested-by: Grygorii Strashko > Signed-off-by: Kishon Vijay Abraham I > Signed-off-by: Sekhar Nori > --- > drivers/pci/dwc/pci-dra7xx.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c > index 34427a6a15af..362607f727ee 100644 > --- a/drivers/pci/dwc/pci-dra7xx.c > +++ b/drivers/pci/dwc/pci-dra7xx.c > @@ -11,6 +11,7 @@ > */ > > #include > +#include > #include > #include > #include > @@ -594,6 +595,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) > int i; > int phy_count; > struct phy **phy; > + struct device_link **link; > void __iomem *base; > struct resource *res; > struct dw_pcie *pci; > @@ -649,11 +651,21 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) > if (!phy) > return -ENOMEM; > > + link = devm_kzalloc(dev, sizeof(*link) * phy_count, GFP_KERNEL); > + if (!link) > + return -ENOMEM; > + > for (i = 0; i < phy_count; i++) { > snprintf(name, sizeof(name), "pcie-phy%d", i); > phy[i] = devm_phy_get(dev, name); > if (IS_ERR(phy[i])) > return PTR_ERR(phy[i]); > + > + link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); > + if (!link[i]) { > + ret = -EINVAL; > + goto err_link; > + } > } > > dra7xx->base = base; > @@ -732,6 +744,10 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) > pm_runtime_disable(dev); > dra7xx_pcie_disable_phy(dra7xx); > > +err_link: > + while (--i >= 0) > + device_link_del(link[i]); > + > return ret; > } > > -- cheers, -roger