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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=V6lwEOni c=1 sm=1 tr=0 ts=69065bca cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=rTtKBu4o5onlnI9juXDqsQ==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=fj3ciZ1XawlKQuAvidcA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: 8jG_Vb2U4bqgiMBAS9TfLHLn5JAbl06l X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTAxMDE2NSBTYWx0ZWRfX2rZ8rstE+AW0 9j2qQbZ0+iCroQRdT+btsfCHnpGM/7nIZ5Zrg0MidtIuQIrE9HFP9lUeEeHpTiDtL+AfIwSQy7K 2YfVqYH/NVD58pGy5gWhPMr/GsnGge9gBRgTZuvQL1l7y2cOf+JIE6JSWJg6KAAtZAgQylPDZA1 G8Oq0kDgVHLQ2q4L1OSQE+AfwPjgvzlin+tw/s/RQrfA/YGMHmi1WueEcW4iBdk4u02i8aYbMMG NVTzpy/V1QqRINRjdavEpTQHY6XJO/0GdWPDhneeU1LGQsTxNOZZBoYIvYjuKqSVy4Idi9TvS5p QdT7VAOh+3cXVKEVE3x7bTaGimZvXgflyvJhNBMlcd5ZAThlU1EP9zM9mtubguVBQqu5joiTDSh T1F6Ha68ub4qmDsZdqQsKA3iFsySTg== X-Proofpoint-ORIG-GUID: 8jG_Vb2U4bqgiMBAS9TfLHLn5JAbl06l X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-01_04,2025-10-29_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 clxscore=1015 adultscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511010165 On 11/1/2025 11:14 PM, Krishna Kurapati wrote: > From: Wesley Cheng > > SM8750 chipset contains a single DWC3 USB3 controller (rev. 200a), SS > QMP PHY (rev. v8) and M31 eUSB2 PHY. The major difference for SM8750 is > the transition to using the M31 eUSB2 PHY compared to previous SoCs. > > Enable USB support on SM8750 MTP and QRD variants. SM8750 has a QMP combo > PHY for the SSUSB path, and a M31 eUSB2 PHY for the HSUSB path. > > Signed-off-by: Wesley Cheng > [Konrad: Provided diff to flattened USB node] > Signed-off-by: Konrad Dybcio > Signed-off-by: Krishna Kurapati > --- > arch/arm64/boot/dts/qcom/sm8750.dtsi | 161 ++++++++++++++++++++++++++- > 1 file changed, 160 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi > index a82d9867c7cb..3f0b57f428bb 100644 > --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi > @@ -12,6 +12,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -635,7 +636,7 @@ gcc: clock-controller@100000 { > <0>, > <0>, > <0>, > - <0>; > + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; > > #clock-cells = <1>; > #reset-cells = <1>; > @@ -2581,6 +2582,164 @@ data-pins { > }; > }; > > + usb_hsphy: phy@88e3000 { > + compatible = "qcom,sm8750-m31-eusb2-phy"; > + reg = <0x0 0x88e3000 0x0 0x29c>; > + > + clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>; > + clock-names = "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > + > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + usb_dp_qmpphy: phy@88e8000 { > + compatible = "qcom,sm8750-qmp-usb3-dp-phy"; > + reg = <0x0 0x088e8000 0x0 0x4000>; > + > + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > + <&tcsrcc TCSR_USB3_CLKREF_EN>, > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > + clock-names = "aux", > + "ref", > + "com_aux", > + "usb3_pipe"; > + > + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, > + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; > + reset-names = "phy", > + "common"; > + > + power-domains = <&gcc GCC_USB3_PHY_GDSC>; > + > + #clock-cells = <1>; > + #phy-cells = <1>; > + > + orientation-switch; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + usb_dp_qmpphy_out: endpoint { > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + usb_dp_qmpphy_usb_ss_in: endpoint { > + remote-endpoint = <&usb_dwc3_ss>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + > + usb_dp_qmpphy_dp_in: endpoint { > + }; > + }; > + }; > + }; > + > + usb: usb@a600000 { > + compatible = "qcom,sm8750-dwc3", "qcom,snps-dwc3"; > + reg = <0x0 0x0a600000 0x0 0xfc100>; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, > + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; > + clock-names = "cfg_noc", > + "core", > + "iface", > + "sleep", > + "mock_utmi"; > + > + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>; > + assigned-clock-rates = <19200000>, > + <200000000>; > + > + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, > + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, > + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "dwc_usb3", > + "pwr_event", > + "hs_phy_irq", > + "dp_hs_phy_irq", > + "dm_hs_phy_irq", > + "ss_phy_irq"; > + > + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; > + required-opps = <&rpmhpd_opp_nom>; Probably I am missing something, but which power domain associated to a rail is scaled to NOM corner here? -Akhil