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Thu, 12 Nov 2026 01:31:56 -0800 (PST) Received: from [10.217.216.70] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b197c9d7c1sm3869051a91.17.2026.11.12.01.31.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Nov 2026 01:31:56 -0800 (PST) Message-ID: Date: Thu, 12 Nov 2026 15:01:32 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 01/10] dt-bindings: ptp: Document the TSCSS on Qualcomm SA8775P and QCS8300 SoCs To: Krzysztof Kozlowski Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Andrew Lunn , "David S. Miller" , Jakub Kicinski , Paolo Abeni , Bjorn Andersson , Konrad Dybcio , Eric Dumazet , Abel Vesa , Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org References: <20261108-tscss-v2-0-d5f575010427@oss.qualcomm.com> <20261108-tscss-v2-1-d5f575010427@oss.qualcomm.com> <20261109-qualified-pristine-newt-ba1c0c@quoll> Content-Language: en-US From: Imran Shaik In-Reply-To: <20261109-qualified-pristine-newt-ba1c0c@quoll> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: 23qtxwwuN-aDFWfABCnbrrOGRAOPx7bf X-Proofpoint-Spam-Info: AW1haW4tMjYxMTEyMDAzNyBTYWx0ZWRfX8Oe5kmdOAVfr XcR794e3JoKM1xoOnhIjz5sNSl4aiYuttS+ADY38PAy/cZjmtAdgptHt8S9dbMrrAoJXkvD170e tp+VKS60yXDvxFL+imKdgO31jrBKUzg= X-Proofpoint-GUID: 23qtxwwuN-aDFWfABCnbrrOGRAOPx7bf X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTEyMDAzNyBTYWx0ZWRfX+QLYK1B8n0wJ Sh/su2o1L4XgqSi3NOznyN8A5JpoOX4ceCVAlyFTQGrA76k+Jzry3kzcQUYU7Lz3vb6pJPRZ6/8 Ff5c6GQPYBmQy+4FRPtP4C09I5KhFUbhLQwWHOowEJneCKeD/oIaNjVQwBULrgOI/C3+nurM8EW Sb7eMM1UmYlW/SkF0DYRuTW/ojcjsMk5NiujM4U+JlWmrEcoL8cWtR6dJgf/HGvw6UHh0U4mANJ IOpYBiODUo/yc5B2OV3L4k/B1+OpkpipMKLiGJqNXu8WBI2HF3UEPSZUQ9Fi1nfSu42b3os/PpH +NQvkGNUy9en2Sau6K2jpZ9RLGr+E3wRwFazaL8fP75xakHng1/w0ys3O+uua8DL9qL3eYuFV6H eeSNkFafm7bN9ZJsqu3EkjFBQ6YTlc0y/hSBgyfbB6zaalOo9ACSbmO8/wo/34/3rL8C/+UN714 zpMgVbkJL9ihdW4S48w== X-Authority-Analysis: v=2.4 cv=A8b5rKWG c=1 sm=1 tr=0 ts=6af5878d cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=-_rbqcG8Jwc29zszMZcA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-12_01,2026-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 spamscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611120037 On 09-11-2026 06:18 pm, Krzysztof Kozlowski wrote: > On Sun, Nov 08, 2026 at 06:48:22PM +0530, Imran Shaik wrote: >> +properties: >> + compatible: >> + oneOf: >> + - const: qcom,sa8775p-tscss >> + - items: >> + - const: qcom,qcs8300-tscss >> + - const: qcom,sa8775p-tscss >> + >> + reg: >> + minItems: 1 >> + maxItems: 2 >> + >> + reg-names: >> + minItems: 1 >> + items: >> + - const: tsc >> + - const: etu > > ... > >> +required: >> + - compatible >> + - reg >> + - reg-names >> + - clocks >> + - clock-names >> + >> +allOf: >> + - if: >> + properties: >> + reg-names: >> + contains: >> + const: etu > > Reason for same devices with different address space details should be > provided somewhere, preferrably in description. Assuming in the first > place, that this stays because how two devices can be basically > identical (same compatible) if they have different programming > interface? > TSCSS is a single hardware device, split into two sub-blocks - TSC and ETU, each with its own register address. Every SoC with this compatible has both blocks in hardware. What changes is whether the vendor/board actually wires up the ETU's external event. The ETU block captures a timestamp from the TSC block when an external event fires one of the ETU slices, which are driven through board-level GPIO/IRQs. If a board doesn't wire any slice, there's nothing in the ETU region for Linux to use. So interrupts/pinctrl/qcom,etu-* only matter once a slice is actually connected. Because of this, only the tsc reg space is described in the DTS patches today. Instead, I'll use the "qcom,etu-slice" property to drive the required constraints, and add reg/reg-names support in DTS by default for both TSC and ETU, and update the description with the above details in the next series. I hope that works. Thanks, Imran