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Fri, 07 Aug 2026 01:07:11 -0700 (PDT) X-Received: by 2002:a17:903:8c5:b0:2c9:e2c1:4fb5 with SMTP id d9443c01a7336-2d106e99159mr91518835ad.22.1786090030918; Fri, 07 Aug 2026 01:07:10 -0700 (PDT) Received: from [10.217.217.28] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d14ccd96afsm5147305ad.24.2026.08.07.01.07.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Aug 2026 01:07:10 -0700 (PDT) Message-ID: Date: Fri, 7 Aug 2026 13:37:02 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/7] iio: adc: qcom-spmi-adc5-gen3: Add support for QCOM PMIC5 Gen4 ADC To: Jonathan Cameron Cc: David Lechner , =?UTF-8?Q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Bjorn Andersson , Konrad Dybcio , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, Kamal Wadhwa , Anjelique Melendez , Manaf Meethalavalappu Pallikunhi , Priyansh Jain References: <20260731-pmic5_gen4_adc-v1-0-9c49b2eea6f9@oss.qualcomm.com> <20260731-pmic5_gen4_adc-v1-2-9c49b2eea6f9@oss.qualcomm.com> <20260803011400.1fb6c93a@jic23-huawei> <20260807001822.31f7c137@jic23-huawei> Content-Language: en-US From: Jishnu Prakash In-Reply-To: <20260807001822.31f7c137@jic23-huawei> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=EYH4hvmC c=1 sm=1 tr=0 ts=6a759230 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=m2Nr5YO-714gfbtmP0IA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-ORIG-GUID: Ee0VK4mRiPPTesOyDg0fO-H9rGC-7qJw X-Proofpoint-GUID: Ee0VK4mRiPPTesOyDg0fO-H9rGC-7qJw X-Proofpoint-Spam-Info: AW1haW4tMjYwODA3MDA1OSBTYWx0ZWRfX/JvMeEdn9OuC sj0afFyInjyNpTMTj47VmOPX4MD+Sji7GalSmkiWTMgDgDTzl2bV9G9VqLQi7ZBBt9L1vT6FOId MO20ZC+JYhmQ7FobkRlTx5hYcH6iexU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA3MDA1OSBTYWx0ZWRfX2OnmxDXC0Ork N+I46FkIrxy5r2XBAPy4uCI0jcZJ2vUF+zm4+NiRAjTBWTyJeW65baa+oodcp6+w2vDGf6U9JpY bvCH/m+hiI2kwRKfzszzzk87wiepKXxf6hOSTVxSnUNVZ3ZIKOyq3mZ7DKihL3w0H0vJZFtuNHm pgtFopeQXn7aDkoyW6NCu2Xby9as5gjQp7adDSyZUi0qTqw+L35fEx/XIjGZ/U3REmZfnaC96vn eLfs0w1NuEENUxa3EXb2u3Avp60tUddb6HZ3MJrFE2X5hFuh7yy9OpGnQ6KoBNNvylyu3OwPh+d T20I9nX+9PXaOrbACo7MSpRa6Hp73BCStl5Yvtmq+/SI1m/7alPJTJ7Coss/UDSVQEVcDC4apSk Ff39+e0rvxDE2gfH1RYR59NxHWeHDvdx8/tmHltQaUOyvk/bNV3DlnyOjc5PcVejwcW4rtI/1Ln 8b7sEoMNYgMRlHks0pA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-07_01,2026-08-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 suspectscore=0 priorityscore=1501 spamscore=0 clxscore=1015 malwarescore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608070059 Hi Jonathan, On 8/7/2026 4:48 AM, Jonathan Cameron wrote: > On Thu, 6 Aug 2026 16:22:16 +0530 > Jishnu Prakash wrote: > >> Hi Jonathan, >> >> On 8/3/2026 5:44 AM, Jonathan Cameron wrote: >>> On Fri, 31 Jul 2026 23:36:15 +0530 >>> Jishnu Prakash wrote: >>> >>>> PMIC5 Gen4 ADC is similar to PMIC5 Gen3 ADC, with several changes made >>>> for improved performance, mostly at the hardware level. >>>> >>>> One significant software change is that ratiometric conversion resolution >>>> has been increased from 14 bits to 16 bits, so the maximum value of >>>> these measurements needs to be updated for Gen4. Add a new scaling >>>> function for thermistor channels which use this type of conversion. >>>> >>>> In the latest PMIC arbiter version (v8), there can be up to 4 buses >>>> under the PMIC arbiter and 32 PMICs under each bus. In order to >>>> support communication between ADC on the master PMIC and ADCs on any >>>> of the other PMICs, a field of width 2 bits is added for bus index >>>> and the bits for SID are extended from 4 to 5 bits, in the SID >>>> register. Add support for this. >>>> >>>> In addition, it is possible that the master PMIC has ADC of one generation >>>> and it needs to communicate with another PMIC with ADC of a different >>>> generation. >>> >>> "Possible" sounds a bit hypothetical. Can we state this actually happens >>> on some devices? >> >> Considering existing upstream platforms, this is applicable for SM8750. I'll >> mention this in the next version of the series. > > What happens on that platform today? Wrong values? Should this be treated > as a fix rather than a feature? There is no issue on that platform right now as ADC channels needing this support are not added yet. SM8750 board files only include pmk8550.dtsi, which has the top-level Gen3 ADC peripheral and some ADC channels on the same PMIC. Gen4 support would be needed only when PMIH0108 ADC channels are added. > > >>>> -static int adc5_gen3_read_voltage_data(struct adc5_chip *adc, u16 *data) >>>> +static int adc5_gen3_read_voltage_data(struct adc5_chip *adc, >>>> + struct adc5_channel_common_prop *prop, >>>> + u16 *data) >>>> { >>>> u8 rslt[2]; >>>> int ret; >>>> @@ -99,8 +101,10 @@ static int adc5_gen3_read_voltage_data(struct adc5_chip *adc, u16 *data) >>>> *data = get_unaligned_le16(rslt); >>>> >>>> if (*data == ADC5_USR_DATA_CHECK) { >>> This feels backwards. We first check for the top bit being >>> set then check whether we care if it is set or not. I think >>> checking if we should look at it first makes more sense. Also >>> shorter max line length: >>> >>> if (!(prop->generation == ADC5_GEN4 && prop->cal_method == ADC5_RATIOMETRIC_CAL)) { >>> if (*data == ADC5_USR_DATA_CHECK) { >>> ... >> >> I thought it was more efficient to have the check like this because >> there may be several channels satisfying the longer if() check for Gen4 >> ratiometric channels, but the chance of *data being exactly equal to >> the error value ADC5_USR_DATA_CHECK is lower generally. So if I reverse >> the checks as you suggested, the outer if() check would pass for every >> read done on a channel which is not both Gen4 and ratiometric, which >> seems inefficient for an error check. >> >> What do you think, should I make any changes here? > > Efficiency here is going to be hard to judge without guessing how good > the prefetchers are and to me this doesn't smell like a performance > critical path. I'd go for clarity of code and check only > for the invalid value after you've established it might actually be > invalid. So change it. Sure, I'll make this change. Thanks, Jishnu > > Thanks, > > Jonathan