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smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=acm.org; spf=pass smtp.mailfrom=acm.org; dkim=pass (2048-bit key) header.d=acm.org header.i=@acm.org header.b=KuUFyIzC; arc=none smtp.client-ip=199.89.3.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=acm.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=acm.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=acm.org header.i=@acm.org header.b="KuUFyIzC" Received: from localhost (localhost [127.0.0.1]) by 004.mia.mailroute.net (Postfix) with ESMTP id 4cmKCz0CpCzm0yTq; Tue, 14 Oct 2025 16:19:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=acm.org; h= content-transfer-encoding:content-type:content-type:in-reply-to :from:from:content-language:references:subject:subject :user-agent:mime-version:date:date:message-id:received:received; s=mr01; t=1760458747; x=1763050748; bh=ezH4sQ6V/nGZXEjHE4GZHEuE J8Dh34wh9XPALEp7pno=; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 10/13/25 11:04 PM, palash.kambar@oss.qualcomm.com wrote: > +static void ufs_qcom_send_command(struct ufs_hba *hba, > + struct ufshcd_lrb *lrbp) > +{ > + struct ufs_qcom_host *host = ufshcd_get_variant(hba); > + unsigned long flags; > + > + if ((host->hw_ver.major == 6 && host->hw_ver.minor == 0 && > + host->hw_ver.step == 0) && hba->mcq_enabled) { > + spin_lock_irqsave(hba->host->host_lock, flags); > + if ((++host->active_cmds) == 1) > + /* Stop the auto-hiberate idle timer */ > + ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER); > + spin_unlock_irqrestore(hba->host->host_lock, flags); > + } > +} Do you realize that obtaining the host lock from the command submission path introduces a contention point and hence cancels one of the benefits of MCQ (different CPU cores can submit commands independently)? This argument still applies if host->active_cmds would be changed into an atomic counter because making that change would still trigger cache line ping-pong if UFS commands are submitted from multiple CPU cores simultaneously. I think this is a strong argument against this patch series. An example of how to implement this kind of counter without killing performance is available in the block layer (&q->q_usage_counter). However, implementing a per-cpu counter and checking in an efficient way whether it has reached zero is much more complicated than the approach of this patch series. Is AHIT really that valuable that you want to sacrifice MCQ performance to enable AHIT? Why not to enable/disable AHIT from the RPM callbacks? Bart.