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From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Brian Masney <bmasney@redhat.com>
Cc: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Chun-Jie Chen <chun-jie.chen@mediatek.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Edward-JW Yang <edward-jw.yang@mediatek.com>,
	Richard Cochran <richardcochran@gmail.com>,
	Chen-Yu Tsai <wenst@chromium.org>,
	kernel@collabora.com, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>,
	Irving-CH Lin <irving-ch.lin@mediatek.com>
Subject: Re: [PATCH v4 00/24] MT8189: Add support for system and base clock controllers
Date: Mon, 14 Sep 2026 15:48:20 +0200	[thread overview]
Message-ID: <f2bb7446-bfbd-4598-ba95-d9561a4e132b@collabora.com> (raw)
In-Reply-To: <aqf6NH-xrMtCQppv@redhat.com>

On 9/14/26 15:44, Brian Masney wrote:
> Hi Angelo,
> 
> On Fri, Jul 31, 2026 at 12:04:49PM +0200, AngeloGioacchino Del Regno wrote:
>> On 7/30/26 20:22, Brian Masney wrote:
>>> Should there be a new MAINTAINERS entry added? There's currently 221
>>> files under drivers/clk/mediatek/ and there's currently only one
>>> mediatek maintainer entry:
>>>
>>>       MEDIATEK MT6735 CLOCK & RESET DRIVERS.
>>>
>>> Is there anyone from mediatek (or elsewhere) that could act as a clk
>>> subsystem maintainer similar to what the other SoC vendors do? Help with
>>> reviews, send in pulls, etc?
>>>
>>
>> I may be able to step in, but I have to check if it's feasible, time-wise, on
>> my side.
>>
>> Though, that won't happen until mid-September... because, well, I'm about to go
>> on holiday (in a few days from now).
> 
> I'm checking in to see if you would be willing to be clk submaintainer
> for the MediaTek clk drivers?
> 
> Brian

Time is lacking, but I get that one hour from me is more than zero, which is
a good thing.

Let's do it.

Cheers,
Angelo

  reply	other threads:[~2026-09-14 13:48 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-29 10:02 Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 01/24] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8186 Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 02/24] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8192 Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 03/24] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8195 Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 04/24] dt-bindings: clock: mediatek: reorder MT8186 compatibles Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 05/24] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 06/24] dt-bindings: clock: mediatek: regroup MT8192 " Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 07/24] dt-bindings: clock: mediatek: regroup MT8195 " Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 08/24] dt-bindings: clock: mediatek: Add MT8189 system/base clocks and resets Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 09/24] clk: mediatek: Harmonize mtk_pll_fenc related symbol names Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 10/24] clk: mediatek: pll: Add BAR reset register offsets Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 11/24] clk: mediatek: pll: split default prepare/unprepare callbacks Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 12/24] clk: mediatek: pll: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 13/24] clk: mediatek: pllfh: Add configurable clock ops to mtk_pllfh_data Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 14/24] clk: mediatek: pllfh: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-07-29 10:02 ` [PATCH v4 15/24] clk: mediatek: Add MT8189 apmixedsys clock support Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 16/24] clk: mediatek: Add MT8189 topckgen " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 17/24] clk: mediatek: Add MT8189 vlpckgen " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 18/24] clk: mediatek: Add MT8189 vlpcfg " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 19/24] clk: mediatek: Add MT8189 bus " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 20/24] clk: mediatek: Add MT8189 dbgao " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 21/24] clk: mediatek: Add MT8189 dvfsrc " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 22/24] clk: mediatek: Add MT8189 i2c " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 23/24] clk: mediatek: Add MT8189 scp " Louis-Alexis Eyraud
2026-07-29 10:03 ` [PATCH v4 24/24] clk: mediatek: Add MT8189 ufs " Louis-Alexis Eyraud
2026-07-30 18:22 ` [PATCH v4 00/24] MT8189: Add support for system and base clock controllers Brian Masney
2026-07-31 10:04   ` AngeloGioacchino Del Regno
2026-09-14 13:44     ` Brian Masney
2026-09-14 13:48       ` AngeloGioacchino Del Regno [this message]
2026-09-14 14:05         ` Brian Masney

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