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Mon, 29 Jun 2026 05:18:38 -0700 (PDT) X-Received: by 2002:a05:6102:32cd:b0:739:64ad:bf4e with SMTP id ada2fe7eead31-73964adc4e6mr249524137.7.1782735517777; Mon, 29 Jun 2026 05:18:37 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-69848e5ebc0sm3117738a12.3.2026.06.29.05.18.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Jun 2026 05:18:36 -0700 (PDT) Message-ID: Date: Mon, 29 Jun 2026 14:18:35 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/3] phy: qcom: qmp-pcie: Add vdda-refgen supply support for Glymur To: Qiang Yu Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260623-phy_refgen-v2-0-4d15983bf91d@oss.qualcomm.com> <8811c181-9caf-4797-8e17-52311702e292@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI5MDEwMSBTYWx0ZWRfXz6dYt338Zwtq Zv7OFMqQrFwV5y2Wz86ffjFroWMzxfE3LohqeyDedyKQaCmU2uPaBDRiW4T7hKfZLNIrnqD8fo0 2nGaLDmxDpYtW/SziS/V3cE9blxBZXs= X-Proofpoint-ORIG-GUID: yPST1YwQcgqUIc-ZeptAJfFSJl9CyQ2L X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI5MDEwMSBTYWx0ZWRfX1E8gCLX1Fvxg JcmUnC+2xIhYs5sfN09B+Xs2ui26buOE3k19uN7abwjRYpXbWzljMhZ8cefgrqGEYn1BruT9eqQ OmUB/p0j4U62qBsVfv0BFVrPrDXhOCZgD3MW+rktOKf4eNPvebjOuPR9JJo+qQ1jZi61P3t01h5 pj5u+HNbR/rkFBRYgAG+JpE55s/1aDe/pSkcdBhZztb220URw33g/UB+3IuyLZ8GAT2ZIlDq6ce NZ8pKXd/stTZt7mgi9aFaP9URcL1IUc0COnraz8T7KiBq9LQqehU7MWoxTv+eJ3iT98nbqtZukv apok1+or1lOA+YPetWWmSiHIFyDxMzW0MYI8eAF29Ghswr+q+pOYMIX3m3vM6F5Aq7bQZWd+IFg NXOqYLHTx2SEkhMU4qoL7XNCE9juN5/uRx4MmwrXfjC2d3Gcd9Nkcfx15aefaoGDgWUvd3fTGuH YxIYsj+Mp0Vj7ecZLtQ== X-Authority-Analysis: v=2.4 cv=NZzWEWD4 c=1 sm=1 tr=0 ts=6a42629f cx=c_pps a=wuOIiItHwq1biOnFUQQHKA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=x4UBAUAyasPmGnV1h00A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=XD7yVLdPMpWraOa8Un9W:22 X-Proofpoint-GUID: yPST1YwQcgqUIc-ZeptAJfFSJl9CyQ2L X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-29_03,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 spamscore=0 adultscore=0 suspectscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606290101 On 6/29/26 2:14 PM, Qiang Yu wrote: > On Mon, Jun 29, 2026 at 12:51:55PM +0200, Konrad Dybcio wrote: >> On 6/23/26 3:05 PM, Qiang Yu wrote: >>> The PCIe QMP PHYs on Glymur require both refgen for stable reference >>> voltage and qref for stable reference clock. The refgen requires two power >>> supplies: vdda-refgen0p9 and vdda-refgen1p2. >>> >>> can be extended in the future. >>> >>> This series creates a Glymur-specific supply list including the refgen >>> supplies and updates both Gen5x4 and Gen4x2 configurations to use it. >>> >>> Signed-off-by: Qiang Yu >>> >>> Changes in v2: >>> - Add dts patch in this series. >>> - Reword commit msg of dtbinding patch. >>> - Link to v1: https://lore.kernel.org/all/20260208-refgen-v1-0-87ca84fd78b3@oss.qualcomm.com/ >>> >>> --- >> >> Is this necessary (for Glymur) now that we correlated some of the >> TCSR clocks with the right nodes? > > This patch is necessary for glymur and mahua and other Qualcomm targets, > which can be verified from the REFGEN page and power grid page on ipcat. > > Take Glymur PCIe3 PHY as an example: it requires two REFGENs — REFGEN0 for > the PHY itself and REFGEN4 for QREF. In the TCSR driver, only the LDOs for > REFGEN4 are voted, not REFGEN0. This is intentional: each consumer is > responsible for voting the LDOs of the REFGEN it uses. Since QREF uses > REFGEN4, the TCSR driver votes the REFGEN4 LDOs; since the PHY uses > REFGEN0, the PHY driver votes the REFGEN0 LDOs. > > For some PHY instances in power grid, you can only see one REFGEN, that > indicates the phy doesn't require QREF or the phy and the QREF it requires > share same REFGEN. >> >> Perhaps this would be necessary for Mahua since its clocks don't >> require QREF (or we can lie about it and handle them there)? > > For Mahua PCIe5 PHY, it doesn't require QREF. So we don't need to vote > REFGEN LDOs for QREF in tcsr driver. But the PHY requires REFGEN. So we > still need to vote in PHY driver. OK, I think I got my mental model of all of this straight. But expect me to make more mistakes and sorry for that! Konrad