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Tue, 21 Jul 2026 00:00:01 -0700 (PDT) X-Received: by 2002:a05:6a20:9145:b0:3b4:b340:411d with SMTP id adf61e73a8af0-3c3ad64da60mr18812449637.24.1784617200719; Tue, 21 Jul 2026 00:00:00 -0700 (PDT) Received: from [10.218.15.172] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-31429ff04absm40704841eec.8.2026.07.20.23.59.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Jul 2026 00:00:00 -0700 (PDT) Message-ID: Date: Tue, 21 Jul 2026 12:29:54 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] arm64: Disallow disabling boot CPU based on config To: Mark Rutland Cc: Thomas Gleixner , Daniel Lezcano , Peter Zijlstra , "Rafael J. Wysocki" , Pavel Machek , Len Brown , Catalin Marinas , Will Deacon , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20260703-disable_boot_cpu_offline-v2-1-782d16ff58c3@oss.qualcomm.com> Content-Language: en-US From: Sneh Mankad In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDA3MSBTYWx0ZWRfXwfvG5vPEwQaK IPBoQMIwTPhzQubo3gPu/KxBhQHyXnAcg/T6kv+lu14qVLD13bIWk6jgyB5mtWJxSzfr7fgkQCa xaicX5bziICJkQdnEhYSNI/+6cAk9jIen4SmYwQdpK+LkjnhAgqwnk1EGFBb5C/ug2ug2V84/RP +LkF6KKzLObSDP2sG8GDSGuFBJzTbAa0GY1gVXbHvSgP0uWgbboYVRoxSmYKRHRFFF1Q6yOt7KR uxYvw4NhS/VVwPq8BqKmMM9x8hddOyuJ+f9KBYpd/NN68hi9eml9fvWTk2I0r709m9EzTNlZWy+ Zq+e+V+qruFjZcl51lEDVjN9GPFuKv+sGu9lWr2PrPtE91SumxGpGRb3B3GNQCptoU13+/sBQpz XpxPUdfyXagU5+RtggMfpH60jWKdR58RwFLwby5a8FqdKAdSYAC0NyBMA4Rnj9Ko1IhwLuWlUq3 Mr+c39BiaXpc2p//vMQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDA3MSBTYWx0ZWRfX6ctsZSTLCRKT u3aNE6I8KcIcbw8sfcRdTQaXAow++xza0FHrwIBe4mB5H2TjLMW+wzSst/UkErAljz5bKTnCJ1F cq7i0rw8CG4tqRP/kvcim7vRyDcqI88= X-Authority-Analysis: v=2.4 cv=WNpPmHsR c=1 sm=1 tr=0 ts=6a5f18f6 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=RLVnq9SYGZ7K_u37rsQA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: ihmKKLGhzzfBERjDmcXd7xk3NeutC5Hj X-Proofpoint-ORIG-GUID: ihmKKLGhzzfBERjDmcXd7xk3NeutC5Hj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_06,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 suspectscore=0 spamscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210071 On 03-Jul-26 7:58 PM, Mark Rutland wrote: > On Fri, Jul 03, 2026 at 04:50:02PM +0530, Sneh Mankad wrote: >> The Qualcomm SoCs like LeMans, Monaco > > Are those released products? Yes, the SoCs are present in upstream: arch/arm64/boot/dts/qcom/lemans.dtsi arch/arm64/boot/dts/qcom/monaco.dtsi > > Are those mobile phone parts, or somthing else? These are ride (automotive) chipsets and IoT boards. > >> support suspend to ram which leads the SoC to ACPI S3 similar state >> where SoC is turned off and DDR is retained. The hardware design on >> these SoCs forces a constraint to suspend and resume the system on >> boot CPU / CPU0. >> >> If CPU0 is already offline before starting suspend to ram the >> freeze_secondary_cpus() picks alternate CPU as primary / last CPU and >> proceed further to invoke PSCI SYSTEM_SUSPEND. >> This leads to a system crash. > > Ok, so that's a firmware bug. > > Why does the FW permit CPU0 to be offlined in the first place if it > can't handle this? FW permits CPU0 disablement because it functions properly in regular run time. But there is an additional hardware constraint in above mentioned platforms, that suspend to ram has to be performed via boot CPU / CPU0. Due to this constraint, CPU0 is required to be online when suspend to ram is triggered. > What does PSCI_MIGRATE_INFO_TYPE report? It is a optional function call, which is not implemented in firmware. > Ideally it'd report Uniprocessor (UP) not migrate capable (1), which > would prevent CPU_OFF on that CPU, and would force suspend to happen > there... Also, above platforms are multicore (8 CPUs each). >> In order to prevent such an issue introduce PM_SLEEP_SMP_CPU_ZERO_STRICT >> config and when enabled prohibit the CPU0 from getting disabled. > > I don't think it makes sense for this to be a config option. > > This is a platform-specific property, and it's possible to build a > kernel that boots on this platform and/or other platforms. Yes, but for that reason the config will only be enabled for SoCs that have this constraint, it will remain disabled for other SoCs. >> Signed-off-by: Sneh Mankad >> --- >> Changes in v2: >> - Moved the check to arm64 specific code. >> - Link to v1: https://lore.kernel.org/r/20260605-disable_boot_cpu_offline-v1-1-4c68fe1a6cf8@oss.qualcomm.com >> --- >> arch/arm64/Kconfig | 9 +++++++++ >> arch/arm64/kernel/psci.c | 6 ++++++ >> 2 files changed, 15 insertions(+) >> >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index fe60738e5943ba279e5571862423df4fed3db661..21697a535a25d286a2f8afe4921a41b13cc32c0a 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -263,6 +263,15 @@ config ARM64 >> help >> ARM 64-bit (AArch64) Linux support. >> >> +config PM_SLEEP_SMP_CPU_ZERO_STRICT >> + bool "Disallow boot CPU (CPU0) offline" >> + depends on ARCH_QCOM > > Why can't others select this? I can remove ARCH_QCOM dependency if any other want to use this. > >> + depends on HOTPLUG_CPU >> + depends on SUSPEND >> + help >> + Disallow boot CPU (CPU0) offline when the suspend_ops->enter() >> + has to be executed by boot CPU. > > As above, I don't think this makse sense as a config option. > > Either we handle the FW bug, or we do not. > > Mark. > As mentioned above, its not a FW bug. CPU0 is allowed to be disabled from FW and HW constraint is for suspend to ram to be performed on boot CPU. Thanks, Sneh