From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF5C5ECAAD3 for ; Fri, 16 Sep 2022 03:34:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229503AbiIPDeq (ORCPT ); Thu, 15 Sep 2022 23:34:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229483AbiIPDej (ORCPT ); Thu, 15 Sep 2022 23:34:39 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4946C55AB; Thu, 15 Sep 2022 20:34:34 -0700 (PDT) X-UUID: fcc5d1b61805480d80e9c56a554ad9b5-20220916 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=uHfb45m1XChImQ98BYTCdPpUchcD7kA9WpfndA6oA2M=; b=gx+8k0NqxKwYgCXSmWyQZzk5BClxrb3McighRkMJuYb0+8E6HdFT9eHAAn3MR0+hbOjBHiG8HV/leBi34xtzWWx2Ob4/aivMBmaYXrGOtFrufjmQUzPQ7f+zaSUtY18gykXtdx86KSVDVicUpJkZRIqaiwwgYuWxDSoxyOZqRWc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:d78917b1-aa95-4643-880a-779e6e1e0ee2,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:39a5ff1,CLOUDID:fe0b98f6-6e85-48d9-afd8-0504bbfe04cb,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: fcc5d1b61805480d80e9c56a554ad9b5-20220916 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1506722192; Fri, 16 Sep 2022 11:34:29 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 16 Sep 2022 11:34:27 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 16 Sep 2022 11:34:27 +0800 Message-ID: Subject: Re: [PATCH v2 1/6] dt-bindings: arm: mediatek: mmsys: change compatible for MT8195 From: Jason-JH Lin To: Matthias Brugger , Chun-Kuang Hu , Rob Herring , "Krzysztof Kozlowski" , AngeloGioacchino Del Regno CC: CK Hu , Rex-BC Chen , "Singo Chang" , Nancy Lin , , , , , , Date: Fri, 16 Sep 2022 11:34:27 +0800 In-Reply-To: References: <20220915161817.10307-1-jason-jh.lin@mediatek.com> <20220915161817.10307-2-jason-jh.lin@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Matthias, Thanks for the review. On Fri, 2022-09-16 at 00:05 +0200, Matthias Brugger wrote: > > On 15/09/2022 18:18, Jason-JH.Lin wrote: > > For previous MediaTek SoCs, such as MT8173, there are 2 display HW > > pipelines binding to 1 mmsys with the same power domain, the same > > clock driver and the same mediatek-drm driver. > > > > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding > > to > > 2 different power domains, different clock drivers and different > > mediatek-drm drivers. > > > > Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR, > > CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture > > Quality) > > and they makes VDOSYS0 supports PQ function while they are not > > including in VDOSYS1. > > > > Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related > > component). It makes VDOSYS1 supports the HDR function while it's > > not > > including in VDOSYS0. > > > > To summarize0: > > Only VDOSYS0 can support PQ adjustment. > > Only VDOSYS1 can support HDR adjustment. > > > > Therefore, we need to separate these two different mmsys hardwares > > to > > 2 different compatibles for MT8195. > > > > Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 > > SoC binding") > > Signed-off-by: Jason-JH.Lin > > Signed-off-by: Bo-Chen Chen > > --- > > .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | > > 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam > > l > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam > > l > > index 6ad023eec193..0e267428eaa6 100644 > > --- > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam > > l > > +++ > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam > > l > > @@ -31,7 +31,7 @@ properties: > > - mediatek,mt8183-mmsys > > - mediatek,mt8186-mmsys > > - mediatek,mt8192-mmsys > > - - mediatek,mt8195-mmsys > > + - mediatek,mt8195-vdosys0 > > Nack, we miss the fallback compatible, as I already said twice. > > Regards, > Matthias I'm sorry this happened again. I'll keep the compatible "mediatek,mt8195-mmsys" at next version. The patch "dt-bindings: arm: mediatek: mmsys: remove the unused compatible for mt8195" should be sent after accepting the vdosys1 series, right? Regards, Jason-JH.Lin > > > - mediatek,mt8365-mmsys > > - const: syscon > > - items: -- Jason-JH Lin