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From: Gatien CHEVALLIER <gatien.chevallier@foss.st.com>
To: Rob Herring <robh@kernel.org>
Cc: "Suzuki K Poulose" <suzuki.poulose@arm.com>,
	"Mike Leach" <mike.leach@linaro.org>,
	"James Clark" <james.clark@linaro.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Mathieu Poirier" <mathieu.poirier@linaro.org>,
	"Leo Yan" <leo.yan@linux.dev>,
	"Clément Le Goffic" <legoffic.clement@gmail.com>,
	"Linus Walleij" <linusw@kernel.org>,
	"Maxime Coquelin" <mcoquelin.stm32@gmail.com>,
	"Alexandre Torgue" <alexandre.torgue@foss.st.com>,
	jens.wiklander@linaro.org, coresight@lists.linaro.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
	linux-stm32@st-md-mailman.stormreply.com
Subject: Re: [PATCH v3 03/12] dt-bindings: bus: document the stm32 debug bus
Date: Thu, 22 Jan 2026 15:13:15 +0100	[thread overview]
Message-ID: <f3250e5e-5fa0-4730-8e0c-14d35bcc0705@foss.st.com> (raw)
In-Reply-To: <20260121152124.GA3179930-robh@kernel.org>



On 1/21/26 16:21, Rob Herring wrote:
> On Wed, Jan 21, 2026 at 01:34:37PM +0100, Gatien Chevallier wrote:
>> Document the stm32 debug bus. The debug bus is responsible for
>> checking the debug sub-system accessibility before probing any related
>> drivers.
>>
>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>> ---
>>   .../bindings/bus/st,stm32mp131-dbg-bus.yaml        | 79 ++++++++++++++++++++++
>>   1 file changed, 79 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml
>> new file mode 100644
>> index 000000000000..2db35e41e76c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml
>> @@ -0,0 +1,79 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/bus/st,stm32mp131-dbg-bus.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: STM32 Coresight bus
>> +
>> +maintainers:
>> +  - Gatien Chevallier <gatien.chevallier@foss.st.com>
>> +
>> +description:
>> +  The STM32 debug bus is in charge of checking the debug configuration
>> +  of the platform before probing the peripheral drivers that rely on the debug
>> +  domain.
>> +
>> +properties:
>> +  compatible:
>> +    items:
>> +      - enum:
>> +          - st,stm32mp131-dbg-bus
>> +          - st,stm32mp151-dbg-bus
>> +
>> +  "#address-cells":
>> +    const: 1
>> +
>> +  "#size-cells":
>> +    const: 1
>> +
>> +  ranges: true
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  "#access-controller-cells":
>> +    const: 1
>> +    description:
>> +      Contains the debug profile necessary to access the peripheral.
>> +
>> +patternProperties:
>> +  "^.*@[0-9a-f]+$":
>> +    description: Debug related peripherals
>> +    type: object
>> +
>> +    additionalProperties: true
>> +
>> +    required:
>> +      - access-controllers
>> +
>> +required:
>> +  - "#access-controller-cells"
>> +  - "#address-cells"
>> +  - "#size-cells"
>> +  - compatible
>> +  - ranges
>> +  - reg
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/clock/stm32mp1-clks.h>
>> +
>> +    dbg_bus: bus@50080000 {
>> +      compatible = "st,stm32mp131-dbg-bus";
>> +      reg = <0x50080000 0x3f80000>;
> 
> That's a lot of registers... Yet the bus driver doesn't access any.
> Looks to me like this belongs in ranges instead if there aren't any bus
> registers. Or its size should be just the registers and then the whole
> region size goes in ranges.
> 

Hello Rob,

Understandable comment. I'll switch to defining the range in the
ranges property in the V3.

Thank you,
Gatien

>> +      #address-cells = <1>;
>> +      #size-cells = <1>;
>> +      #access-controller-cells = <1>;
>> +      ranges;
>> +
>> +      cs_cti_trace: cti@50094000 {
>> +        compatible = "arm,coresight-cti", "arm,primecell";
>> +        reg = <0x50094000 0x1000>;
>> +        clocks = <&rcc CK_DBG>;
>> +        clock-names = "apb_pclk";
>> +        access-controllers = <&dbg_bus 0>;
>> +      };
>> +    };
>>
>> -- 
>> 2.43.0
>>


  reply	other threads:[~2026-01-22 14:15 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-21 12:34 [PATCH v3 00/12] bus: add stm32 debug bus and coresight support for stm32mp1x platforms Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 01/12] dt-bindings: document access-controllers property for coresight peripherals Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 02/12] dt-bindings: pinctrl: document access-controllers property for stm32 HDP Gatien Chevallier
2026-01-27  9:20   ` Linus Walleij
2026-01-21 12:34 ` [PATCH v3 03/12] dt-bindings: bus: document the stm32 debug bus Gatien Chevallier
2026-01-21 15:21   ` Rob Herring
2026-01-22 14:13     ` Gatien CHEVALLIER [this message]
2026-01-21 12:34 ` [PATCH v3 04/12] bus: stm32_firewall: allow check on different firewall controllers Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 05/12] bus: stm32_firewall: add stm32_firewall_get_grant_all_access() API Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 06/12] drivers: bus: add the stm32 debug bus driver Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 07/12] arm: dts: stm32: introduce the debug bus for stm32mp1x platforms Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 08/12] arm: dts: stm32: enable the debug bus on stm32mp1x boards Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 09/12] arm: dts: stm32: enable CoreSight on stm32mp15xx-dkx boards Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 10/12] arm: dts: stm32: enable CoreSight on the stm32mp157c-ev1 board Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 11/12] arm: dts: stm32: enable CoreSight on the stm32mp135f-dk board Gatien Chevallier
2026-01-21 12:34 ` [PATCH v3 12/12] pinctrl: stm32: add firewall checks before probing the HDP driver Gatien Chevallier

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