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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2446d57e140sm8982125ad.156.2025.08.15.01.30.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 Aug 2025 01:30:16 -0700 (PDT) Message-ID: Date: Fri, 15 Aug 2025 16:30:08 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 03/13] dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: support dual TCSR registers To: Krzysztof Kozlowski , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, fange.zhang@oss.qualcomm.com, quic_lliu6@quicinc.com, quic_yongmou@quicinc.com References: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> <20250722-add-displayport-support-for-qcs615-platform-v2-3-42b4037171f8@oss.qualcomm.com> <2fd202a6-2c92-469c-81c0-8852562d4e35@kernel.org> From: Xiangxu Yin In-Reply-To: <2fd202a6-2c92-469c-81c0-8852562d4e35@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=G6EcE8k5 c=1 sm=1 tr=0 ts=689ef01a cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=6sAUhDfBEk1Dn3Xrvb0A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDA5NyBTYWx0ZWRfX7I7PSSXGcDg5 erZS4695yJzS1gUFUY+JREB92pOCt0ynRCCMOkOEUy5eNQ0T44d6YWTxubOhwR75IjBoXqQq3tI MqmXN7l6n0MxlBY0Ac90GYHNj4hBFZnCrIPTdl/EXlQyIk4jiXD4DlFbpgzP947vNrl25ZbeeyP 36kehdk/EPH1JcwMofvslNfM1+ZwqW6ZA0UMjBqrAySO0KV1J/ACk2/yGiTOC9PigZnvKjlNyoL hjeQ4r6enak/Vnyj3o5Hudiif9gxVaRr9WTJCmsBn+dRyLvD23YuWPK9IDaE9sPoMab1ICzCcIP KcuRbE/EVyq8crF7P8SiOz7khKzrpoql6ZvRw1UJiIOfY4Dbcgr80zeDeBYty4f9cfB/NaZWs2F JdsuxEF3 X-Proofpoint-ORIG-GUID: BpObskBPGdg07vTcaC7MrytxX7dveAjU X-Proofpoint-GUID: BpObskBPGdg07vTcaC7MrytxX7dveAjU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-15_03,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 phishscore=0 malwarescore=0 adultscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110097 On 7/22/2025 5:19 PM, Krzysztof Kozlowski wrote: > On 22/07/2025 09:22, Xiangxu Yin wrote: >> Add support for specifying two TCSR register addresses in the >> qcom,tcsr-reg property to enable DP-only mode switching. This change >> maintains backward compatibility with the original single-register >> format. >> >> Also update #clock-cells and #phy-cells to <1> to support clock and PHY >> provider interfaces, respectively. This is required for platforms that >> consume the PHY clock and select PHY mode dynamically. >> >> Signed-off-by: Xiangxu Yin >> --- >> .../bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | 28 +++++++++++++++++----- >> 1 file changed, 22 insertions(+), 6 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml >> index 1636285fbe535c430fdf792b33a5e9c523de323b..badfc46cda6c3a128688ac63b00d97dc2ba742d6 100644 >> --- a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml >> +++ b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml >> @@ -44,13 +44,21 @@ properties: >> vdda-pll-supply: true >> >> "#clock-cells": >> - const: 0 >> + oneOf: >> + - description: Set to 0 for legacy platforms without clock provider >> + const: 0 >> + - description: Set to 1 to expose PHY pipe clock. >> + const: 1 >> >> clock-output-names: >> maxItems: 1 >> >> "#phy-cells": >> - const: 0 >> + oneOf: >> + - description: Set to 0 for legacy platforms >> + const: 0 >> + - description: Set to 1 to supports mode selection (e.g. USB/DP) >> + const: 1 > I don't understand why EXISTING platforms now get more clocks. What did > you change in the hardware? This you must explain in the commit msg. > > > Best regards, > Krzysztof As discussed in [PATCH v2 02/13], I misunderstood Dmitry's intent regarding backward compatibility in v1.  This part will be dropped in the next patch to avoid affecting existing platform configurations. Thanks for pointing it out.