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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aff138a8c1dsm1235771166b.99.2025.09.03.08.33.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Sep 2025 08:33:45 -0700 (PDT) Message-ID: Date: Wed, 3 Sep 2025 17:33:41 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 9/9] arm64: dts: qcom: Add MST pixel streams for displayport To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Abel Vesa , Mahadevan , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski References: <20250903-dp_mst_bindings-v8-0-7526f0311eaa@oss.qualcomm.com> <20250903-dp_mst_bindings-v8-9-7526f0311eaa@oss.qualcomm.com> <964a58d4-ddb6-4c98-9283-1769c0f11204@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Ycq95xRf c=1 sm=1 tr=0 ts=68b85fdb cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=xrVuZHS62xsaktVfuFIA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-GUID: xoTNNNh0n3CGQ0I8lNpkX64ZxGQNUT2u X-Proofpoint-ORIG-GUID: xoTNNNh0n3CGQ0I8lNpkX64ZxGQNUT2u X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTAxMDEwMSBTYWx0ZWRfX723kmvytoFp0 HggXBTOFD8wme15oRPGn1+FUSF997G29MBp8u6ZIknu3uC5NTd+eM/7JdArP7tseUZ4pjZsJWWc bX5gmAZLL6lexMO2gkLmGqdJls9/EXO4z3OzxMbQ8bK/pl6QBT/YbZQgcAFL+xfqd2qyfntEiMr g6iyz+4pBdcbchwy48h7nkoXB7GqSXd2TzqzVhrV94OJq8/twghYxx0L6D6i6k/xQuE/vSpGDiQ MFc6DE9TlMw7E4rMMJURxYgyUtP+zhxm0rhIGQfiaL0vQc3cIG9T+xQpdrZLcRpOsd/5ybNLRm7 kLQVffmFJCzW4tiUXWEPVAR7TzcivUisW3Wnv5/bG3xvyAr9Aij2HMtAe547b/VIzEw6aHs6UJF OPRvzHJg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-03_08,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 malwarescore=0 bulkscore=0 suspectscore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509010101 On 9/3/25 3:58 PM, Dmitry Baryshkov wrote: > On Wed, Sep 03, 2025 at 03:41:45PM +0200, Konrad Dybcio wrote: >> On 9/3/25 1:58 PM, Dmitry Baryshkov wrote: >>> From: Jessica Zhang >>> >>> Update Qualcomm DT files in order to declare extra stream pixel clocks >>> and extra register resources used on these platforms to support >>> DisplayPort MST. >>> >>> The driver will continue to work with the old DTS files as even after >>> adding MST support the driver will have to support old DTS files which >>> didn't have MST clocks. >>> >>> Signed-off-by: Jessica Zhang >>> Signed-off-by: Dmitry Baryshkov >>> --- >> >> [...] >> >>> diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi >>> index 70c87c79e1325f4ab4c81f34e99c0b52be4b3810..e6a7248040095077d6f98d632f4e8a1868432445 100644 >>> --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi >>> @@ -3241,16 +3241,20 @@ mdss_dp0: displayport-controller@ae90000 { >>> <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, >>> <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, >>> <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, >>> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; >>> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, >>> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; >>> clock-names = "core_iface", >>> "core_aux", >>> "ctrl_link", >>> "ctrl_link_iface", >>> - "stream_pixel"; >>> + "stream_pixel", >>> + "stream_1_pixel"; >>> >>> assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, >>> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; >>> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, >>> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; >>> assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, >>> + <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, >>> <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; >>> >>> phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>; >>> @@ -3319,16 +3323,20 @@ mdss_dp1: displayport-controller@ae98000 { >>> <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, >>> <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, >>> <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, >>> - <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>; >>> + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>, >>> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; >>> clock-names = "core_iface", >>> "core_aux", >>> "ctrl_link", >>> "ctrl_link_iface", >>> - "stream_pixel"; >>> + "stream_pixel", >>> + "stream_1_pixel"; >>> >>> assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, >>> - <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; >>> + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>, >>> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; >>> assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, >>> + <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, >>> <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; >> >> Something's not right here > > No, it's correct as far as I understand. On this platform INTF3 / PIXEL1 > is shared between INTF0 / PIXEL and INTF4 / PIXEL2. So it is > counterintuitive, but seems to be correct. Eh, I unfortunately found confirmation for what you said. Hopefully this doesn't cause too much extra pain on the driver side Konrad