RE: [PATCH v4] mtd: spi-nor: micron-st: Add support for is25wx01g

[<Takahiro.Kuwano@infineon.com>]

Hi,

> Add support for the ISSI IS25WX01G, a 1 Gbit (128 MiB) octal NOR flash.
> The part is fully described by SFDP, so only the flash ID and small
> post_bfpt and post_sfdp fixups are needed.
> 
> WRITE STATUS REGISTER (01h) takes a single data byte and only affects
> status register bits 7:2, so the default 16-bit Write Status assumption
> does not hold. Clear write_sr1_and_sr2 so that the single byte write_sr1
> path is taken; write_sr1 is already set to 01h by the BFPT parsing.
> 
> The flash also has no Status Register 2. Configuration registers are read
> with B5h/85h and written with B1h/81h, and the 35h Read Configuration
> Register command does not exist, so clear read_sr2 as well.
> 
> Software write protection is done through the block protect bits in the
> status register: BP0-BP2 at bits 4:2, BP3 at bit 6 and a Top/Bottom bit at
> bit 5, which is exactly what SPI_NOR_HAS_LOCK, SPI_NOR_4BIT_BP,
> SPI_NOR_BP3_SR_BIT6 and SPI_NOR_HAS_TB describe, so set those flags to get
> the generic locking support.
> 
> The flash also supports 8D-8D-8D, but this could not be tested. Since the
> SFDP has no SCCR map, the core would select 8D-8D-8D on a capable
> controller but never switch the flash into it. Hence, drop the 8D-8D-8D
> capabilities in a post_sfdp fixup for now.
> 
To fix missing SCCR map,
	.fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE
is needed.

Could you check if it works?

Thanks,
Takahiro