From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: "Minda Chen" <minda.chen@starfivetech.com>,
"Emil Renner Berthing" <emil.renner.berthing@canonical.com>,
"Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Philipp Zabel <p.zabel@pengutronix.de>,
Mason Huo <mason.huo@starfivetech.com>,
Leyfoon Tan <leyfoon.tan@starfivetech.com>,
Kevin Xie <kevin.xie@starfivetech.com>
Subject: Re: [PATCH v1 1/3] dt-binding: pci: add JH7110 PCIe dt-binding documents.
Date: Mon, 10 Apr 2023 17:21:22 +0200 [thread overview]
Message-ID: <f37964c6-0a75-2900-e6a7-282f5366696c@linaro.org> (raw)
In-Reply-To: <430f1eb0-e348-8a4e-b501-16b8c3b2494f@starfivetech.com>
On 10/04/2023 11:05, Minda Chen wrote:
>>> +
>>> + starfive,stg-syscon:
>>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>>> + items:
>>> + items:
>>> + - description: phandle to System Register Controller stg_syscon node.
>>> + - description: register0 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
>>> + - description: register1 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
>>> + - description: register2 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
>>> + - description: register3 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
>>> + description:
>>> + The phandle to System Register Controller syscon node and the offset
>>> + of STG_SYSCONSAIF__SYSCFG register for PCIe. Total 4 regsisters offset
>>> + for PCIe.
>>> +
>>> + pwren-gpios:
>>> + description: Should specify the GPIO for controlling the PCI bus device power on.
>>
>> What are these? Different than defined in gpio-consumer-common?
>>
> power gpio board level configuration. It it not a requried property
What is "board level configuration"? Again - is it different than
powerdown-gpios from gpio-consumer-common.yaml?
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-04-10 15:21 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-06 11:11 [PATCH v1 0/3] Add JH7110 PCIe driver support Minda Chen
2023-04-06 11:11 ` [PATCH v1 1/3] dt-binding: pci: add JH7110 PCIe dt-binding documents Minda Chen
2023-04-06 18:24 ` Krzysztof Kozlowski
2023-04-06 18:35 ` Conor Dooley
2023-04-06 18:45 ` Conor Dooley
2023-04-06 18:52 ` Krzysztof Kozlowski
2023-04-07 3:45 ` Minda Chen
2023-04-10 9:05 ` Minda Chen
2023-04-10 15:21 ` Krzysztof Kozlowski [this message]
2023-04-11 7:45 ` Minda Chen
2023-04-12 10:17 ` Bin Meng
2023-04-06 11:11 ` [PATCH v1 2/3] pcie: starfive: add StarFive JH7110 PCIe driver Minda Chen
2023-04-06 11:11 ` [PATCH v1 3/3] riscv: dts: starfive: add PCIe dts configuration for JH7110 Minda Chen
2023-04-06 18:25 ` Krzysztof Kozlowski
2023-04-06 11:47 ` [PATCH v1 0/3] Add JH7110 PCIe driver support Conor Dooley
2023-04-06 11:54 ` Conor Dooley
2023-04-07 2:32 ` Minda Chen
2023-04-07 9:57 ` Conor Dooley
2023-04-10 8:58 ` Minda Chen
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