From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A81AECDE32 for ; Wed, 17 Oct 2018 08:40:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4F1F6214C3 for ; Wed, 17 Oct 2018 08:40:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="OKpro9VX" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4F1F6214C3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727014AbeJQQfR (ORCPT ); Wed, 17 Oct 2018 12:35:17 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:12675 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726112AbeJQQfR (ORCPT ); Wed, 17 Oct 2018 12:35:17 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 17 Oct 2018 01:40:36 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 17 Oct 2018 01:40:39 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 17 Oct 2018 01:40:39 -0700 Received: from [10.26.11.110] (172.20.13.39) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 17 Oct 2018 08:40:35 +0000 Subject: Re: [PATCH v1 1/5] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 To: Dmitry Osipenko , Thierry Reding , Peter De Schrijver , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring CC: , , , References: <20180830194356.14059-1-digetx@gmail.com> <20180830194356.14059-2-digetx@gmail.com> From: Jon Hunter Message-ID: Date: Wed, 17 Oct 2018 09:40:32 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <20180830194356.14059-2-digetx@gmail.com> X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL103.nvidia.com (172.20.187.11) To HQMAIL101.nvidia.com (172.20.187.10) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1539765636; bh=5479PAn8B21mYjXb1RFGFSHZlLg4Dq3JAWIRSY3CK0g=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=OKpro9VXastNq4Lmqx9yba9NvpfMqnPFSdtDHJ8MQl5pUpX+M+KPLGfCYHu5NhdYd YmLMxHw7DI4taxgsyKthMfeQvmGPhaSHNcagZspLUcl3YIHgiEIqxN10NCBUJvWRRd QtnYb5aOiI6fGgpzeffkikxRU319jGpJ0AsUQGu8inE7sh7MHbmxxYQjrAUMISL9RC 2URWgTkBhW8yfvcLoUlECc31kxituDmgtud1/pdYKYiqPg0Myab1Vk4xBCHcQTpTVh el5Almjka2593QPmQWajxFXYJ8oZAx1QZ6e8mCDMdrrAO+KoCIWFMLnxuNSiH3UsvL HRRiHx47A8W1Q== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 30/08/2018 20:43, Dmitry Osipenko wrote: > Add device-tree binding that describes CPU frequency-scaling hardware > found on NVIDIA Tegra20/30 SoC's. > > Signed-off-by: Dmitry Osipenko > --- > .../cpufreq/nvidia,tegra20-cpufreq.txt | 38 +++++++++++++++++++ > 1 file changed, 38 insertions(+) > create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt > > diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt > new file mode 100644 > index 000000000000..2c51f676e958 > --- /dev/null > +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt > @@ -0,0 +1,38 @@ > +Binding for NVIDIA Tegra20 CPUFreq > +================================== > + > +Required properties: > +- clocks: Must contain an entry for each entry in clock-names. > + See ../clocks/clock-bindings.txt for details. > +- clock-names: Must include the following entries: > + - pll_x: main-parent for CPU clock, must be the first entry > + - backup: intermediate-parent for CPU clock > + - cpu: the CPU clock Is it likely that 'backup' will be anything other that pll_p? If not why not just call it pll_p? Personally, I don't 'backup' to descriptive even though I can see what you mean. I can see that you want to make this flexible, but if the likelihood is that we will just use pll_p then I am not sure it is warranted at this point. Cheers Jon -- nvpublic