Re: [PATCH v2 1/3] KVM: x86/pmu: Stop adding speculative Intel GP PMCs that don't exist yet

[Like Xu <like.xu.linux@gmail.com>]

On 8/9/2022 12:33 am, Jim Mattson wrote:
> On Wed, Sep 7, 2022 at 3:48 AM Like Xu <like.xu.linux@gmail.com> wrote:
>>
>> From: Like Xu <likexu@tencent.com>
>>
>> The Intel April 2022 SDM - Table 2-2. IA-32 Architectural MSRs adds
>> a new architectural IA32_OVERCLOCKING_STATUS msr (0x195), plus the
>> presence of IA32_CORE_CAPABILITIES (0xCF), the theoretical effective
>> maximum value of the Intel GP PMCs is 14 (0xCF - 0xC1) instead of 18.
>>
>> But the conclusion of this speculation "14" is very fragile and can
>> easily be overturned once Intel declares another meaningful arch msr
>> in the above reserved range, and even worse, Intel probably put PMCs
>> 8-15 in a completely different range of MSR indices.
> 
> The last clause is just conjecture.
> 
>> A conservative proposal would be to stop at the maximum number of Intel
>> GP PMCs supported today. Also subsequent changes would limit both AMD
>> and Intel on the number of GP counter supported by KVM.
>>
>> There are some boxes like Intel P4 may indeed have 18 counters, but
>> those counters are in a completely different msr address range and do
>> not strictly adhere to the Intel Arch PMU specification, and will not
>> be supported by KVM in the near future.
> 
> The P4 PMU isn't virtualized by KVM today, is it?

According to [1], P4 PMU has ZERO number of Intel Architectural Events, and
the KVM support for non Intel Arch PMUs has been dropped recently.

[1] 
https://www.intel.com/content/dam/develop/external/us/en/documents/30320-nehalem-pmu-programming-guide-core.pdf

> 
>>
>> Cc: Vitaly Kuznetsov <vkuznets@redhat.com>
>> Suggested-by: Jim Mattson <jmattson@google.com>
>> Signed-off-by: Like Xu <likexu@tencent.com>
> 
> Please put the "Fixes" tag back. You convinced me that it should be there.
> 
> Reviewed-by: Jim Mattson <jmattson@google.com>