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([2a01:e0a:106d:1080:73bc:1eca:d39e:509]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439b1b97927sm37622495f8f.28.2026.03.05.07.57.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Mar 2026 07:57:55 -0800 (PST) Message-ID: Date: Thu, 5 Mar 2026 16:57:54 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: Neil Armstrong Subject: Re: [PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder To: Krzysztof Kozlowski , Zhentao Guo , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org References: <20260213-b4-s4-vdec-upstream-v4-0-c7112d00d662@amlogic.com> <20260213-b4-s4-vdec-upstream-v4-1-c7112d00d662@amlogic.com> <75e55ceb-e6dd-47b5-a829-66f6fbb3e13e@amlogic.com> <2f68ee18-e9d9-4da6-900c-93a7663b3c9d@kernel.org> <598c161c-d157-40e5-992c-912540589d7e@amlogic.com> <58d57a6c-7c69-4f5b-a4c2-f34ef0238511@kernel.org> <26d0f52e-3681-46ce-b0dc-0cb020e8d9a1@amlogic.com> <69900d76-3820-467a-9fbc-13f79189df2f@kernel.org> <278f5018-9183-4eeb-bde1-7c19adecab06@linaro.org> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 3/5/26 12:53, Krzysztof Kozlowski wrote: > On 05/03/2026 12:35, Neil Armstrong wrote: >> On 3/5/26 12:08, Krzysztof Kozlowski wrote: >>> On 05/03/2026 12:01, Zhentao Guo wrote: >>>> >>>> 2. Why canvas is needed? >>>> >>>> 1. Since the ARM IOMMU HW is not integrated into the Amlogic SOCs,we >>>> need canvas to prevent the DDR memory used by the decoder from being >>>> rewrote by other hardware. Canvas provides the decoder with a >>>> configurable DDR memory range, as well as hardware-based detection >>>> and blocking for out-of-bounds access. >>>> 2. From the diagram above, we can see a lite CPU called AMRISC. AMRISC >>>> is the controller of the decoder HW and the decoder driver needs to >>>> access the decoder hardware through AMRISC. However, AMRISC is a >>>> 16-bit CPU and cannot directly handle 32-bit or 64-bit physical >>>> addresses. Therefore, canvas is required to convert the addresses >>>> into index to facilitate processing by the AMRISC core. >>> >>> This suggests "Canvas" is IOMMU, thus use proper IOMMU abstractions and >>> you cannot have own phandle for it. >> >> >> No it is not, canvas was used for a long time for the display and video processing side. >> >> It's absolutely not like an IOMMU, the diagram is quite clear. > > The diagram and all descriptions points to memory mapping... > > "Canvas index is basically a reference to a memory region and its > configurations." > "Memory access through canvas has HW out-of-boundary check." > "Canvas provides the decoder with a configurable DDR memory range" > "canvas is required to convert the addresses into index to..." > > so it is not a random phandle either. No mapping is done by the Canvas HW, we simply reserve a "slot" we feed with a linear buffer allocated by ourselves + parameters on the frame format, and then the display engine or the video decoder will only need this slot index to access the memory. It doesn't fine anywhere and amlogic specific. Neil > > > Best regards, > Krzysztof