From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S940200AbdAFLTb (ORCPT ); Fri, 6 Jan 2017 06:19:31 -0500 Received: from foss.arm.com ([217.140.101.70]:42548 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S940155AbdAFLSn (ORCPT ); Fri, 6 Jan 2017 06:18:43 -0500 Subject: Re: [PATCH v3 7/9] arm64: cpufeature: Track user visible fields To: Catalin Marinas References: <1483552147-9605-1-git-send-email-suzuki.poulose@arm.com> <1483552147-9605-8-git-send-email-suzuki.poulose@arm.com> <20170105180626.GH29765@e104818-lin.cambridge.arm.com> Cc: linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com, ryan.arnold@linaro.org, sid@reserved-bit.com, aph@redhat.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, adhemerval.zanella@linaro.org, dave.martin@arm.com From: Suzuki K Poulose Message-ID: Date: Fri, 6 Jan 2017 11:18:39 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <20170105180626.GH29765@e104818-lin.cambridge.arm.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/01/17 18:06, Catalin Marinas wrote: > On Wed, Jan 04, 2017 at 05:49:05PM +0000, Suzuki K. Poulose wrote: >> Track the user visible fields of a CPU feature register. This will be >> used for exposing the value to the userspace. All the user visible >> fields of a feature register will be passed on as it is, while the >> others would be filled with their respective safe value. >> >> Cc: Catalin Marinas >> Cc: Will Deacon >> Cc: Mark Rutland >> Signed-off-by: Suzuki K Poulose > > Reviewed-by: Catalin Marinas > >> @@ -81,75 +82,75 @@ cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused) >> >> >> static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { >> - ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0), >> - ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), >> - ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), >> - ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), >> - ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), >> - ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0), On a second look, I think we should make the RDM field visible to the user space as it is something useful for the user. >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), > > BTW, as a separate patch I think we need to expose the RDM field in this > register as well, together with a corresponding HWCAP bit. OK, I will send a separate patch for this. Thanks for the review. Suzuki