From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752960AbcKEFtZ (ORCPT ); Sat, 5 Nov 2016 01:49:25 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:35658 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751524AbcKEFtX (ORCPT ); Sat, 5 Nov 2016 01:49:23 -0400 Subject: Re: [PATCH v2] phy: sun4i: check PMU presence when poking unknown bit of pmu To: Hans de Goede , , Maxime Ripard , Chen-Yu Tsai References: <20161028162701.4531-1-icenowy@aosc.xyz> <41f43381-c1bb-2f69-5f99-ac5cebf651ea@redhat.com> CC: , , From: Kishon Vijay Abraham I Message-ID: Date: Sat, 5 Nov 2016 11:18:37 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: <41f43381-c1bb-2f69-5f99-ac5cebf651ea@redhat.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Friday 28 October 2016 11:45 PM, Hans de Goede wrote: > Hi, > > On 28-10-16 18:27, Icenowy Zheng wrote: >> Allwinner SoC's PHY 0, when used as OTG controller, have no pmu part. >> The code that poke some unknown bit of PMU for H3/A64 didn't check >> the PHY, and will cause kernel oops when PHY 0 is used. >> >> This patch will check whether the pmu is not NULL before poking. >> >> Fixes: b3e0d141ca9f (phy: sun4i: add support for A64 usb phy) >> >> Signed-off-by: Icenowy Zheng >> Acked-by: Maxime Ripard > > Patch LGTM too: > > Reviewed-by: Hans de Goede merged, thanks. -Kishon > > Regards, > > Hans > > >> --- >> drivers/phy/phy-sun4i-usb.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c >> index b9342a2..fec34f5 100644 >> --- a/drivers/phy/phy-sun4i-usb.c >> +++ b/drivers/phy/phy-sun4i-usb.c >> @@ -264,7 +264,7 @@ static int sun4i_usb_phy_init(struct phy *_phy) >> return ret; >> } >> >> - if (data->cfg->enable_pmu_unk1) { >> + if (phy->pmu && data->cfg->enable_pmu_unk1) { >> val = readl(phy->pmu + REG_PMU_UNK1); >> writel(val & ~2, phy->pmu + REG_PMU_UNK1); >> } >>