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charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAxOCBTYWx0ZWRfX2O9HZKUjROLg 3uiZ93gKTl+jEquOcGeCkrwHZfY0Q2oKZg5IazT0nAS7dzn3z7Uq6VRxEw3IJraLhnTUo9ZQ6YZ JJF0U1aytk3Af+Ch4eOU9mnDcElFMvDkcmdsE8j+XpDXCqHNpZ1KjsslBmIkz1cJjFBApw+9VEY mBY/GWvp4Lrmmx41srOh8Ka4ymUYlLn0RilMmmKILh3iqzm+FeQSzjuzzKtF5jP2P3r4BGF/KDF UKlHu53iZrO8unRLcQakxLeOlNhuzsLuxz0EPrymMbSgW7W+rNvuJ5FoaTVDBb6MJ+U6APXWHcN MFrdw8tuUFUWsMcVUWpDH5zisTMAyElCw0fKF52tCb6D58LaP4TMoTKLqkyZVx5cOMtDXFU9r75 HcdWZQKN X-Proofpoint-ORIG-GUID: NLmm28vDa_4MoLjZ_Ddp84iPMtsK1eir X-Authority-Analysis: v=2.4 cv=bvpMBFai c=1 sm=1 tr=0 ts=68d13207 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=Uz3yg00KUFJ2y2WijEJ4bw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=XVeZa78dugChcG7OFuEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: NLmm28vDa_4MoLjZ_Ddp84iPMtsK1eir X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-22_01,2025-09-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 bulkscore=0 clxscore=1015 suspectscore=0 malwarescore=0 impostorscore=0 adultscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200018 On 9/22/2025 5:45 PM, Dmitry Baryshkov wrote: > On Mon, Sep 22, 2025 at 02:58:17PM +0800, Xiangxu Yin wrote: >> On 9/20/2025 2:41 AM, Dmitry Baryshkov wrote: >>> On Fri, Sep 19, 2025 at 10:24:29PM +0800, Xiangxu Yin wrote: >>>> Add QCS615-specific configuration for USB/DP PHY, including DP init >>>> routines, voltage swing tables, and platform data. Add compatible >>>> "qcs615-qmp-usb3-dp-phy". >>>> >>>> Signed-off-by: Xiangxu Yin >>>> --- >>>> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 395 +++++++++++++++++++++++++++++++ >>>> 1 file changed, 395 insertions(+) >>>> >>>> + >>>> + writel(0x3f, qmp->dp_tx + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN); >>>> + writel(0x10, qmp->dp_tx + QSERDES_V2_TX_HIGHZ_DRVR_EN); >>>> + writel(0x0a, qmp->dp_tx + QSERDES_V2_TX_TX_POL_INV); >>>> + writel(0x3f, qmp->dp_tx2 + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN); >>>> + writel(0x10, qmp->dp_tx2 + QSERDES_V2_TX_HIGHZ_DRVR_EN); >>>> + writel(0x0a, qmp->dp_tx2 + QSERDES_V2_TX_TX_POL_INV); >>> Are you sure that these don't need to be adjusted based on >>> qmp->orientation or selected lanes count? >>> >>> In fact... I don't see orientation handling for DP at all. Don't we need >>> it? >> >> Thanks for the review. >> >> I agree with your reasoning and compared talos 14nm HPG with hana/kona >> 7nm PHY HPG; the 7nm COMBO PHY series has orientation/lane-count dependent >> configs, but the 14nm PHY series does not. On QCS615 (talos), the TX_* >> registers you pointed to are programmed with constant values regardless >> of orientation or lane count. This has been confirmed from both the HPG >> and the downstream reference driver. > Thanks for the confirmation. > >> For orientation, from reference the only difference is DP_PHY_MODE, which >> is set by qmp_usbc_configure_dp_mode(). The DP PHY does have an >> SW_PORTSELECT-related register, but due to talos lane mapping from the >> DP controller to the PHY not being the standard <0 1 2 3> sequence, it >> cannot reliably handle orientation flip. Also, QCS615 is a fixed- >> orientation platform (not DP-over-TypeC), so there is no validated hardware >> path for orientation flip on this platform. > Wait... I thought that the the non-standard lane order is handled by the > DP driver, then we should be able to handle the orientation inside PHY > driver as usual. Yes, I have confirmed this with our verification team. For the non-standard lane order, handling flip requires swapping mapped  lane 0 ↔ lane 3 and lane 1 ↔ lane 2 in the logical2physical mapping. This is a hardware limitation, and with the current PHY driver we cannot propagate orientation status to dp_ctrl for processing. > Anyway, please add a FIXME comment into the source file and a note to > the commit message that SW_PORTSELECT should be handled, but it's not a > part of this patch for the stated reasons. OK, I will add a |FIXME| comment in |qmp_usbc_dp_power_on| and update the related commit message. >> >>>> + >>>> + writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); >>>> + writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); >>>> + >>>> + if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V2_DP_PHY_STATUS, >>>> + status, >>>> + ((status & BIT(1)) > 0), >>>> + 500, >>>> + 10000)){ >>>> + dev_err(qmp->dev, "PHY_READY not ready\n"); >>>> + return -ETIMEDOUT; >>>> + } >>>> + >>>> + return 0; >>>> +} >>>> +