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charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AC:EE_|MN2PR12MB4143:EE_ X-MS-Office365-Filtering-Correlation-Id: b8e5534a-af33-4b45-5e75-08dbef691e50 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QwntImEPaDFrrNvTNHfpAV2XALwprX5rlITR9t0+BI+ctWtcTrH5OD7lOZ9nIU8mqQQd1zuhXMh9NI4DE1ytAnSk8SLfHdDwWX/Lda56kYoHXfoSYS2P9Uq6VTF10vqJC8kkohTSl/sItSOm/oGp0JgFeBKjbniPOuxSPqqbZCanWQYU8tc1dMo6FwU4m12bVOpyoGOU3GU4dgejOavOPbHCAOizJOQp7RZEA94Dt7Yq7Lcg6scwkOh903lpg7JK06XB0s1UZzAqTFa5gLpI4PtbHersnhPUXdW59TYkxzR+YbDffTB7aZc1zGx01GPI2O+vB+le7wdF6J4rYNpREz9NeaLsjEnfS7jZ5SL/aXUwWes4VC5SSyeI77sxPp6bhenNAn5M7lRjaQJpb29G3GBwNIN1yG/vgo8zUXt0RSjM1Fjky4I1WL9Vz/Ni3X9ThQPGeqk8Wjm3/j7HmD99fC6/w87/5mW/O1UDvg/bMpv4me5SFd5D4Qp21fN3CbWNGEX64F8uuDAexu5axCjBoWO/RZ7LeIp/xVkwYBjTVTaJnXzhClfo/NwBn2fUJb5Tu/rz2qIuSrmeY14vrhwLjh1vqUyUCYXDGWs5m6kjw+lJuPYAxmnbqXh4q7k3uB1vvR9LUM2ZtgjOto7e8bZL2yBsC6C5L7pCoAYvHDDhsfSir176AWgzk3aWZ0Ub/Fpbq0Z5Axdv+g+lZY/rC8Q51sbdv3E2oBHhsRNGurkk8PO9zmm3neGiZyUTdxOx/90VHvhYy8BT6m73WVUneJ45XL+UI7qDVAgn137POL8H6M6c9Mjh5oe0YNxZt4banOm4 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(396003)(136003)(39860400002)(346002)(230922051799003)(1800799012)(82310400011)(186009)(451199024)(64100799003)(46966006)(40470700004)(36840700001)(44832011)(2906002)(31686004)(36860700001)(8936002)(8676002)(41300700001)(26005)(70206006)(316002)(6636002)(16576012)(110136005)(70586007)(53546011)(5660300002)(336012)(426003)(2616005)(40480700001)(83380400001)(47076005)(356005)(81166007)(86362001)(31696002)(82740400003)(478600001)(36756003)(40460700003)(36900700001)(43740500002);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Nov 2023 16:51:36.0682 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b8e5534a-af33-4b45-5e75-08dbef691e50 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4143 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/27/23 08:43, Lizhi Hou wrote: > > On 11/24/23 11:25, Jan Kuliga wrote: >> According to the XDMA datasheet (PG195), the address of any descriptor >> must be 32 byte aligned. The datasheet also states that a contiguous >> block of descriptors must not cross a 4k address boundary. Therefore, >> it is possible to ease the pressure put on the dma_pool allocator >> just by requiring sufficient alignment and boundary values. Add proper >> macro definition and change the values passed into the >> dma_pool_create(). >> >> Signed-off-by: Jan Kuliga >> --- >>   drivers/dma/xilinx/xdma-regs.h | 7 ++++--- >>   drivers/dma/xilinx/xdma.c      | 6 +++--- >>   2 files changed, 7 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/dma/xilinx/xdma-regs.h >> b/drivers/dma/xilinx/xdma-regs.h >> index 6bf7ae84e452..d5cb12e6b8d4 100644 >> --- a/drivers/dma/xilinx/xdma-regs.h >> +++ b/drivers/dma/xilinx/xdma-regs.h >> @@ -64,9 +64,10 @@ struct xdma_hw_desc { >>       __le64        next_desc; >>   }; >>   -#define XDMA_DESC_SIZE        sizeof(struct xdma_hw_desc) >> -#define XDMA_DESC_BLOCK_SIZE    (XDMA_DESC_SIZE * XDMA_DESC_ADJACENT) >> -#define XDMA_DESC_BLOCK_ALIGN    4096 >> +#define XDMA_DESC_SIZE            sizeof(struct xdma_hw_desc) >> +#define XDMA_DESC_BLOCK_SIZE        (XDMA_DESC_SIZE * >> XDMA_DESC_ADJACENT) >> +#define XDMA_DESC_BLOCK_ALIGN        32 >> +#define XDMA_DESC_BLOCK_BOUNDARY    4096 >>     /* >>    * Channel registers >> diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c >> index de4615bd4ee5..d32ae93e18b6 100644 >> --- a/drivers/dma/xilinx/xdma.c >> +++ b/drivers/dma/xilinx/xdma.c >> @@ -735,9 +735,9 @@ static int xdma_alloc_chan_resources(struct >> dma_chan *chan) >>           return -EINVAL; >>       } >>   -    xdma_chan->desc_pool = dma_pool_create(dma_chan_name(chan), >> -                           dev, XDMA_DESC_BLOCK_SIZE, >> -                           XDMA_DESC_BLOCK_ALIGN, 0); >> +    xdma_chan->desc_pool = dma_pool_create(dma_chan_name(chan), dev, >> +                XDMA_DESC_BLOCK_SIZE, XDMA_DESC_BLOCK_ALIGN, >> +                        XDMA_DESC_BLOCK_BOUNDARY); >>       if (!xdma_chan->desc_pool) { >>           xdma_err(xdev, "unable to allocate descriptor pool"); >>           return -ENOMEM; > > This is probably not needed. The 32 adjacent descriptors here is 1024 > bytes. Defining 4k alignment should be good enough. Oh, Just noticed the you have changed the alignment to 32. Sorry, I just hit send too quick. > > Thanks, > > Lizhi > >