From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751971AbdFTByy (ORCPT ); Mon, 19 Jun 2017 21:54:54 -0400 Received: from mga02.intel.com ([134.134.136.20]:23890 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751036AbdFTByw (ORCPT ); Mon, 19 Jun 2017 21:54:52 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,363,1493708400"; d="scan'208";a="1184581282" Subject: Re: [PATCH v2 3/3] perf report: Implement visual marker for macro fusion in annotate To: Arnaldo Carvalho de Melo Cc: Jiri Olsa , Peter Zijlstra , mingo@infradead.org, alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org, ak@linux.intel.com, kan.liang@intel.com, yao.jin@intel.com References: <1497840958-4759-1-git-send-email-yao.jin@linux.intel.com> <1497840958-4759-4-git-send-email-yao.jin@linux.intel.com> <20170619173529.GM3645@kernel.org> <13d15de3-419c-22b1-1699-fdcc766117eb@linux.intel.com> <20170620013742.GE13640@kernel.org> From: "Jin, Yao" Message-ID: Date: Tue, 20 Jun 2017 09:54:36 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: <20170620013742.GE13640@kernel.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >> Reference for macro fusion is the optimization guide, >> http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html >> 2.3.2.1 >> — In Intel microarchitecture code name Nehalem: CMP, TEST. >> — In Intel microarchitecture code name Sandy Bridge: CMP, TEST, ADD, SUB, >> AND, INC, DEC >> — These instructions can fuse if The first source / destination operand is a >> register. >> >> The second source operand (if exists) is one of: immediate, register, or non >> RIP-relative memory. >> The second instruction of the macro-fusable pair is a conditional branch. >> >> We probably don't need the full rules, just a simple test for >> CMP/TEST/ADD/SUB/AND/INC/DEC and second instruction a Jcc condition branch. >> Also I don't think we need to distinguish Nehalem/Sandy Bridge and other >> core platforms. A simple test may be acceptable. > Humm, then we need to make sure somehow that this may or may not be > happening, with the above rules and optimization guide URL and pages > mentioned in the documentation. > > I think that as we improve the disassembler, the more precise we can go > the better. If we know that the machine is x86 _and_ Nehalem, then we > should do this fusing visual cue onlyu for CMP and TEST, etc. > > - Arnaldo > I will add checking for Nehalem (CMP, TEST). For other newer Intel CPUs just check it by default (CMP, TEST, ADD, SUB, AND, INC, DEC). Thanks Jin Yao