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[2a02:a466:4d7a:0:49c0:3675:3f69:8ee2]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b83926533b7sm450609966b.20.2025.12.30.18.58.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 30 Dec 2025 18:58:34 -0800 (PST) Message-ID: Date: Wed, 31 Dec 2025 03:58:33 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 0/2] PCI: Configure Root Port MPS during host probing To: Hans Zhang <18255117159@163.com>, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, heiko@sntech.de, mani@kernel.org, yue.wang@Amlogic.com Cc: pali@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, jingoohan1@gmail.com, khilman@baylibre.com, jbrunet@baylibre.com, martin.blumenstingl@googlemail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org References: <20251127170908.14850-1-18255117159@163.com> Content-Language: en-US From: Ricardo Pardini In-Reply-To: <20251127170908.14850-1-18255117159@163.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 27/11/2025 18:09, Hans Zhang wrote: > Current PCIe initialization exhibits a key optimization gap: Root Ports > may operate with non-optimal Maximum Payload Size (MPS) settings. While > downstream device configuration is handled during bus enumeration, Root > Port MPS values inherited from firmware or hardware defaults often fail > to utilize the full capabilities supported by controller hardware. This > results in suboptimal data transfer efficiency throughout the PCIe > hierarchy. > > This patch series addresses this by: > > 1. Core PCI enhancement (Patch 1): > - Proactively configures Root Port MPS during host controller probing > - Sets initial MPS to hardware maximum (128 << dev->pcie_mpss) > - Conditional on PCIe bus tuning being enabled (PCIE_BUS_TUNE_OFF unset) > and not in PCIE_BUS_PEER2PEER mode (which requires default 128 bytes) > - Maintains backward compatibility via PCIE_BUS_TUNE_OFF check > - Preserves standard MPS negotiation during downstream enumeration > > 2. Driver cleanup (Patch 2): > - Removes redundant MPS configuration from Meson PCIe controller driver > - Functionality is now centralized in PCI core > - Simplifies driver maintenance long-term > > --- > Changes in v7: > - Exclude PCIE_BUS_PEER2PEER mode from Root Port MPS configuration > - Remove redundant check for upstream bridge (Root Ports don't have one) > - Improve commit message and code comments as per Bjorn. Hi Hans, I've tested on an Odroid-HC4 with a SATA SSD (via an ASM1061) by applying your v7 on v6.19-rc3 + Bjorn's 20251103221930.1831376-1-helgaas@kernel.org ("PCI: meson: Remove meson_pcie_link_up() timeout, message, speed check" which is required to get the meson PCIe to work at all since 6.18). With that setup I get: # hdparm --direct -t /dev/sda Timing O_DIRECT disk reads: 832 MB in 3.00 seconds = 277.33 MB/sec I've an identical machine, with a similar disk (even slightly faster, on paper), running plain 6.12.y and there I get: # hdparm --direct -t /dev/sda Timing O_DIRECT disk reads: 764 MB in 3.00 seconds = 254.26 MB/sec I repeated those a few times, not very scientific, I know; but anyway: Tested-by: Ricardo Pardini # on Odroid-HC4 I've also feedback from another user running with this series with success on a different meson PCIe machine, will ask them to TB as well; they had reported a significant drop in performance since v6.18 without this. Thanks, Ricardo