From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFBFD179BD; Sun, 14 Apr 2024 05:59:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.196 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713074379; cv=none; b=MnTeJTaSYPxthVv/qu/MIypqoDluEs+zRNtlA5g2CcfWoFBXXgl4zZLM+VasvPWsO8uXl/XVLiB0Zk/tr+ajGsN2YhKlwNKCeXMEgJQinapW0v5khykWVkayYEKHPJYWyzUV9UCk4X1Bb4DlMafLQ40UVO3dP+WhVIEbvHNZeqI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713074379; c=relaxed/simple; bh=+F9SE9a2hneMWBPdTbXkuw6pE8D5bqSVAmLAV1tq13Y=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=TdZ7JEmFE+GKZ3lDqBnaUQFLXBylS4c8kQd6x8CCxe4tS1yZ9p2avldJGCJVOVfBiuBzAwzDb2duQeVKuxG+URjgNqUSN6s/vTzQWo8f5kLYyfJIXLFJ0GyLQPHG3z75g/pjSRu8APTfmy5HVvpg9LoD7E9FVQbL0S2qdEErdaQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arinc9.com; spf=pass smtp.mailfrom=arinc9.com; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b=Njoqy5Ng; arc=none smtp.client-ip=217.70.183.196 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arinc9.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arinc9.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="Njoqy5Ng" Received: by mail.gandi.net (Postfix) with ESMTPSA id A1F44E0002; Sun, 14 Apr 2024 05:59:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1713074369; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DkAVfJhrb20IYkFdMPZ7uw1ETykugiPubMA1XaxEiMQ=; b=Njoqy5NgTDA6NbHuTAtH3AtByQBGjYShG+Bi5WaBWSlEI+xUoDFNc/CXuhNv9anFPfulab gb7EBw9Ydxa5LDoEWQdyiw0CRVG9qaMskqreRlmFwmYvEkJPmFK0jx1FWX44ZkfyEtounA eKOpYraemv4ZCjooEJdmbTDhGD/Zq4W5PTb4gtARvLpOafS4OHofhKPWwe06Rjcu0B4okw THU8GsDRRv9FuFU/tBZFn1+O5mAcwrq45RUgQ18iV43P8bDGcancaU7V9RP/E+AlrFc+Bm omzgfykL5m+7IabFWjQshiaJEbwheJpBhQimpPlMZAbfGW/rleFLRSW7+zMZGg== Message-ID: Date: Sun, 14 Apr 2024 08:59:11 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next 1/2] net: dsa: mt7530-mdio: read PHY address of switch from device tree To: Daniel Golle Cc: DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org References: <20240414-b4-for-netnext-mt7530-phy-addr-from-dt-and-simplify-core-ops-v1-0-b08936df2770@arinc9.com> <20240414-b4-for-netnext-mt7530-phy-addr-from-dt-and-simplify-core-ops-v1-1-b08936df2770@arinc9.com> Content-Language: en-US From: =?UTF-8?B?QXLEsW7DpyDDnE5BTA==?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-GND-Sasl: arinc.unal@arinc9.com On 14.04.2024 06:10, Daniel Golle wrote: > On Sun, Apr 14, 2024 at 01:08:19AM +0300, Arınç ÜNAL via B4 Relay wrote: >> From: Arınç ÜNAL >> >> Read the PHY address the switch listens on from the reg property of the >> switch node on the device tree. This change brings support for MT7530 >> switches on boards with such bootstrapping configuration where the switch >> listens on a different PHY address than the hardcoded PHY address on the >> driver, 31. >> >> As described on the "MT7621 Programming Guide v0.4" document, the MT7530 >> switch and its PHYs can be configured to listen on the range of 7-12, >> 15-20, 23-28, and 31 and 0-4 PHY addresses. >> >> There are operations where the switch PHY registers are used. For the PHY >> address of the control PHY, transform the MT753X_CTRL_PHY_ADDR constant >> into a macro and use it. The PHY address for the control PHY is 0 when the >> switch listens on 31. In any other case, it is one greater than the PHY >> address the switch listens on. >> >> Signed-off-by: Arınç ÜNAL > > See minor nit inline below. > > Reviewed-by: Daniel Golle > Tested-by: Daniel Golle > (only MT7530 and MT7531 on address 0x1f has been tested, I don't have > any board configuring the switch to any other base-address) > >> --- >> drivers/net/dsa/mt7530-mdio.c | 28 ++++++++++++++-------------- >> drivers/net/dsa/mt7530.c | 35 ++++++++++++++++++++++------------- >> drivers/net/dsa/mt7530.h | 4 +++- >> 3 files changed, 39 insertions(+), 28 deletions(-) >> >> diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h >> index 585db03c0548..76adc9d21bcf 100644 >> --- a/drivers/net/dsa/mt7530.h >> +++ b/drivers/net/dsa/mt7530.h >> @@ -625,7 +625,7 @@ enum mt7531_clk_skew { >> #define MT7531_PHY_PLL_OFF BIT(5) >> #define MT7531_PHY_PLL_BYPASS_MODE BIT(4) >> >> -#define MT753X_CTRL_PHY_ADDR 0 >> +#define MT753X_CTRL_PHY_ADDR(phy_addr) (phy_addr == 0x1f ? 0 : phy_addr + 1) > > #define MT753X_CTRL_PHY_ADDR(phy_addr) (phy_addr + 1 & 0x1f) > > It's shorter, and works without conditional operator which is expensive. Great, thanks. Arınç