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Message-ID: <f568fd917bb8789fcef4206e256ef045176605e2.camel@xry111.site>
Subject: Re: [PATCH] LoongArch: Improve memory ops
From:   Xi Ruoyao <xry111@xry111.site>
To:     Rui Wang <wangrui@loongson.cn>
Cc:     Huacai Chen <chenhuacai@kernel.org>,
        WANG Xuerui <kernel@xen0n.name>, loongarch@lists.linux.dev,
        linux-kernel@vger.kernel.org, loongson-kernel@lists.loongnix.cn
Date:   Mon, 10 Apr 2023 22:37:56 +0800
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On Mon, 2023-04-10 at 22:19 +0800, Rui Wang wrote:
> On Mon, Apr 10, 2023 at 8:20=E2=80=AFPM Xi Ruoyao <xry111@xry111.site> wr=
ote:
> >=20
> > On Mon, 2023-04-10 at 19:57 +0800, WANG rui wrote:
> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* align up address */
> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 andi=C2=A0=C2=A0=C2=A0 t1, a0, =
7
> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sub.d=C2=A0=C2=A0 a0, a0, t1
> >=20
> > bstrins.d a0, zero, 2, 0
> >=20
> > Likewise for other aligning operations if the temporary is not used.
>=20
> I think we're on the same page. I had previously tested this on the
> user-space version[1], but it's not a performance-critical area.

The point is "if you can reduce one instruction and one register usage
with no harm, why not do it?" :)

AFAIK bstrins.d should be available on all 64-bit LoongArch CPUs.


--=20
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University