From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758016AbdJKUKA (ORCPT ); Wed, 11 Oct 2017 16:10:00 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:38874 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757852AbdJKUJy (ORCPT ); Wed, 11 Oct 2017 16:09:54 -0400 X-Google-Smtp-Source: AOwi7QABn4xe0cHf8Eeo5dquPdr9ra0V0xw7lCCx43NM3fM9huX+SD5uheGDjrilAyXZGqGtHEnRCg== From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Greg Kroah-Hartman , Rob Herring , Mauro Carvalho Chehab , Stephen Warren Cc: Dan Carpenter , linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, devel@driverdev.osuosl.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/2] ARM: dts: tegra20: Add video decoder node Date: Wed, 11 Oct 2017 23:08:12 +0300 Message-Id: X-Mailer: git-send-email 2.14.2 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a device node for the video decoder engine found on Tegra20. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 7c85f97f72ea..1b5d54b6c0cb 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -249,6 +249,23 @@ */ }; + vde@6001a000 { + compatible = "nvidia,tegra20-vde"; + reg = <0x6001a000 0x3D00 /* VDE registers */ + 0x40000400 0x3FC00>; /* IRAM region */ + reg-names = "regs", "iram"; + interrupts = , /* UCQ error interrupt */ + , /* Sync token interrupt */ + , /* BSE-V interrupt */ + , /* BSE-A interrupt */ + ; /* SXE interrupt */ + interrupt-names = "ucq-error", "sync-token", "bsev", "bsea", "sxe"; + clocks = <&tegra_car TEGRA20_CLK_VDE>; + clock-names = "vde"; + resets = <&tegra_car 61>; + reset-names = "vde"; + }; + apbmisc@70000800 { compatible = "nvidia,tegra20-apbmisc"; reg = <0x70000800 0x64 /* Chip revision */ -- 2.14.2