From: Stafford Horne <shorne@gmail.com>
To: Jonas Bonn <jonas@southpole.se>,
Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Cc: linux@roeck-us.net, openrisc@lists.librecores.org,
linux-kernel@vger.kernel.org, Stafford Horne <shorne@gmail.com>
Subject: [PATCH v2 02/23] openrisc: add cache way information to cpuinfo
Date: Sat, 4 Feb 2017 00:48:26 +0900 [thread overview]
Message-ID: <f5a80de3896ed5022247e5d691f0ea41335bb3ef.1486135912.git.shorne@gmail.com> (raw)
In-Reply-To: <cover.1486135912.git.shorne@gmail.com>
In-Reply-To: <cover.1486135912.git.shorne@gmail.com>
From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Motivation for this is to be able to print the way information
properly in print_cpuinfo(), instead of hardcoding it to one.
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Signed-off-by: Jonas Bonn <jonas@southpole.se>
[shorne@gmail.com fixed conflict with show_cpuinfo change]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/include/asm/cpuinfo.h | 2 ++
arch/openrisc/kernel/setup.c | 67 ++++++++++++++++++++-----------------
2 files changed, 38 insertions(+), 31 deletions(-)
diff --git a/arch/openrisc/include/asm/cpuinfo.h b/arch/openrisc/include/asm/cpuinfo.h
index 917318b..ec10679 100644
--- a/arch/openrisc/include/asm/cpuinfo.h
+++ b/arch/openrisc/include/asm/cpuinfo.h
@@ -24,9 +24,11 @@ struct cpuinfo {
u32 icache_size;
u32 icache_block_size;
+ u32 icache_ways;
u32 dcache_size;
u32 dcache_block_size;
+ u32 dcache_ways;
};
extern struct cpuinfo cpuinfo;
diff --git a/arch/openrisc/kernel/setup.c b/arch/openrisc/kernel/setup.c
index cb797a3..dbf5ee9 100644
--- a/arch/openrisc/kernel/setup.c
+++ b/arch/openrisc/kernel/setup.c
@@ -117,13 +117,15 @@ static void print_cpuinfo(void)
if (upr & SPR_UPR_DCP)
printk(KERN_INFO
"-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n",
- cpuinfo.dcache_size, cpuinfo.dcache_block_size, 1);
+ cpuinfo.dcache_size, cpuinfo.dcache_block_size,
+ cpuinfo.dcache_ways);
else
printk(KERN_INFO "-- dcache disabled\n");
if (upr & SPR_UPR_ICP)
printk(KERN_INFO
"-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n",
- cpuinfo.icache_size, cpuinfo.icache_block_size, 1);
+ cpuinfo.icache_size, cpuinfo.icache_block_size,
+ cpuinfo.icache_ways);
else
printk(KERN_INFO "-- icache disabled\n");
@@ -155,25 +157,25 @@ void __init setup_cpuinfo(void)
{
struct device_node *cpu;
unsigned long iccfgr, dccfgr;
- unsigned long cache_set_size, cache_ways;
+ unsigned long cache_set_size;
cpu = of_find_compatible_node(NULL, NULL, "opencores,or1200-rtlsvn481");
if (!cpu)
panic("No compatible CPU found in device tree...\n");
iccfgr = mfspr(SPR_ICCFGR);
- cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
+ cpuinfo.icache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
cpuinfo.icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
cpuinfo.icache_size =
- cache_set_size * cache_ways * cpuinfo.icache_block_size;
+ cache_set_size * cpuinfo.icache_ways * cpuinfo.icache_block_size;
dccfgr = mfspr(SPR_DCCFGR);
- cache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
+ cpuinfo.dcache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
cpuinfo.dcache_block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
cpuinfo.dcache_size =
- cache_set_size * cache_ways * cpuinfo.dcache_block_size;
+ cache_set_size * cpuinfo.dcache_ways * cpuinfo.dcache_block_size;
if (of_property_read_u32(cpu, "clock-frequency",
&cpuinfo.clock_frequency)) {
@@ -308,30 +310,33 @@ static int show_cpuinfo(struct seq_file *m, void *v)
revision = vr & SPR_VR_REV;
seq_printf(m,
- "cpu\t\t: OpenRISC-%x\n"
- "revision\t: %d\n"
- "frequency\t: %ld\n"
- "dcache size\t: %d bytes\n"
- "dcache block size\t: %d bytes\n"
- "icache size\t: %d bytes\n"
- "icache block size\t: %d bytes\n"
- "immu\t\t: %d entries, %lu ways\n"
- "dmmu\t\t: %d entries, %lu ways\n"
- "bogomips\t: %lu.%02lu\n",
- version,
- revision,
- loops_per_jiffy * HZ,
- cpuinfo.dcache_size,
- cpuinfo.dcache_block_size,
- cpuinfo.icache_size,
- cpuinfo.icache_block_size,
- 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
- 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW),
- 1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
- 1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW),
- (loops_per_jiffy * HZ) / 500000,
- ((loops_per_jiffy * HZ) / 5000) % 100);
-
+ "cpu\t\t: OpenRISC-%x\n"
+ "revision\t: %d\n"
+ "frequency\t: %ld\n"
+ "dcache size\t: %d bytes\n"
+ "dcache block size\t: %d bytes\n"
+ "dcache ways\t: %d\n"
+ "icache size\t: %d bytes\n"
+ "icache block size\t: %d bytes\n"
+ "icache ways\t: %d\n"
+ "immu\t\t: %d entries, %lu ways\n"
+ "dmmu\t\t: %d entries, %lu ways\n"
+ "bogomips\t: %lu.%02lu\n",
+ version,
+ revision,
+ loops_per_jiffy * HZ,
+ cpuinfo.dcache_size,
+ cpuinfo.dcache_block_size,
+ cpuinfo.dcache_ways,
+ cpuinfo.icache_size,
+ cpuinfo.icache_block_size,
+ cpuinfo.icache_ways,
+ 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
+ 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW),
+ 1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
+ 1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW),
+ (loops_per_jiffy * HZ) / 500000,
+ ((loops_per_jiffy * HZ) / 5000) % 100);
return 0;
}
--
2.9.3
next prev parent reply other threads:[~2017-02-03 15:49 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-03 15:48 [PATCH v2 00/23] OpenRISC patches from backlog for 4.11 Stafford Horne
2017-02-03 15:48 ` [PATCH v2 01/23] openrisc: use SPARSE_IRQ Stafford Horne
2017-02-03 15:48 ` Stafford Horne [this message]
2017-02-03 15:48 ` [PATCH v2 03/23] openrisc: tlb miss handler optimizations Stafford Horne
2017-02-03 15:48 ` [PATCH v2 04/23] openrisc: head: use THREAD_SIZE instead of magic constant Stafford Horne
2017-02-03 15:48 ` [PATCH v2 05/23] openrisc: head: refactor out tlb flush into it's own function Stafford Horne
2017-02-03 15:48 ` [PATCH v2 06/23] openrisc: add l.lwa/l.swa emulation Stafford Horne
2017-02-03 15:48 ` [PATCH v2 07/23] openrisc: add atomic bitops Stafford Horne
2017-02-03 15:48 ` [PATCH v2 08/23] openrisc: add cmpxchg and xchg implementations Stafford Horne
2017-02-03 15:48 ` [PATCH v2 09/23] openrisc: add optimized atomic operations Stafford Horne
2017-02-03 15:48 ` [PATCH v2 10/23] openrisc: add spinlock implementation Stafford Horne
2017-02-03 15:48 ` [PATCH v2 11/23] openrisc: add futex_atomic_* implementations Stafford Horne
2017-02-03 15:48 ` [PATCH v2 12/23] openrisc: remove unnecessary stddef.h include Stafford Horne
2017-02-03 15:48 ` [PATCH v2 13/23] openrisc: Fix the bitmask for the unit present register Stafford Horne
2017-02-03 15:48 ` [PATCH v2 14/23] openrisc: Initial support for the idle state Stafford Horne
2017-02-03 15:48 ` [PATCH v2 15/23] openrisc: Add optimized memset Stafford Horne
2017-02-03 15:48 ` [PATCH v2 16/23] openrisc: Add optimized memcpy routine Stafford Horne
2017-02-03 15:48 ` [PATCH v2 17/23] openrisc: Add .gitignore Stafford Horne
2017-02-03 15:48 ` [PATCH v2 18/23] MAINTAINERS: Add the openrisc official repository Stafford Horne
2017-02-03 15:48 ` [PATCH v2 19/23] scripts/checkstack.pl: Add openrisc support Stafford Horne
2017-02-03 15:48 ` [PATCH v2 20/23] openrisc: entry: Whitespace and comment cleanups Stafford Horne
2017-02-03 15:48 ` [PATCH v2 21/23] openrisc: entry: Fix delay slot detection Stafford Horne
2017-02-03 15:48 ` [PATCH v2 22/23] openrisc: head: Move init strings to rodata section Stafford Horne
2017-02-03 15:48 ` [PATCH v2 23/23] arch/openrisc/lib/memcpy.c: use correct OR1200 option Stafford Horne
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