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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8044f4acdbsm3534554166b.22.2025.12.30.06.30.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 30 Dec 2025 06:30:40 -0800 (PST) Message-ID: Date: Tue, 30 Dec 2025 15:30:36 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/4] arm64: dts: qcom: Introduce Glymur base dtsi To: Pankaj Patil , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, rajendra.nayak@oss.qualcomm.com, sibi.sankar@oss.qualcomm.com, Jyothi Kumar Seerapu , Maulik Shah , Taniya Das , Kamal Wadhwa , Prudhvi Yarlagadda , Qiang Yu , Manaf Meethalavalappu Pallikunhi , Jishnu Prakash , Abel Vesa References: <20251219-upstream_v3_glymur_introduction-v3-0-32271f1f685d@oss.qualcomm.com> <20251219-upstream_v3_glymur_introduction-v3-3-32271f1f685d@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20251219-upstream_v3_glymur_introduction-v3-3-32271f1f685d@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=POcCOPqC c=1 sm=1 tr=0 ts=6953e213 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=w7Tv4zNA8aCE7STyPtkA:9 a=G0Cx74KbSqDmYbrs:21 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-ORIG-GUID: LAjkIzD3xmsUjhnLS4Gz2Idg4uNQkC72 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjMwMDEzMSBTYWx0ZWRfX612QFBnW2mdG nI1hXd61dASSjCc1GkHrHHAHIKpGX5FxF/yXbVLcgenm5r48yRLZjOKhAPqASds++IJQlZBqBT+ kiRGQSMBEf5kVFrO6xPbB9YdWR+KNwY57CIsCO4QWVTIdzsFNpEfYJskfnrkt5tIdfeYURSQr+x nukBMfn1ePW5hdymLOKKbqtdKHlFjhO78HhyR7DHQfQuqpauT3Z0pHF/GnQ8VxO6/8VhTWCKUvO q0R2KNWB2YrGmthH8rvfwqO4oT4mqIrgY/6rw9cXKUDA8pm1pLnyyMwjVs+C5RMQZw4CoCLahMS WjonIFBSzC+Rq9qv/yLnjfZTgx/OpHTM9EMeQhu0wdFI0yCprLJoFlo7Ea+91LvHRFOpK48dvG4 OZN+vMMiQAzDERu947oQmKIPNDQCT1UmkQyY2ZUW/UiIfE6VS2krc+SgetjXP30Jq+J53B0AyAy WD2LqoFGTL5cTW3Zd5Q== X-Proofpoint-GUID: LAjkIzD3xmsUjhnLS4Gz2Idg4uNQkC72 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-30_01,2025-12-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 bulkscore=0 phishscore=0 clxscore=1015 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512300131 On 12/19/25 3:46 PM, Pankaj Patil wrote: > Introduce the base device tree support for Glymur – Qualcomm's > next-generation compute SoC. The new glymur.dtsi describes the core SoC > components, including: [...] > + gpi_dma2: dma-controller@800000 { > + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; > + reg = <0x0 0x00800000 0x0 0x60000>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + dma-channels = <16>; > + dma-channel-mask = <0x3f>; > + #dma-cells = <3>; > + iommus = <&apps_smmu 0xd76 0x0>; > + status = "disabled"; Any reason for it to be disabled? On some platforms the (common and default) TZ config is overzealous, but that shouldn't generally be the case on compute. > + }; > + > + qupv3_2: geniqup@8c0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0x008c0000 0x0 0x3000>; > + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; > + clock-names = "m-ahb", > + "s-ahb"; > + iommus = <&apps_smmu 0xd63 0x0>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "disabled"; Similarly here (individual QUPs should stay disabled because leaving them all enabled would lead to multiple attempts at claiming the same pins) [...] > + reg-names = "parf", > + "dbi", > + "elbi", > + "atu", > + "config", > + "mhi"; > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x01000000 0x0 0x00000000 0x0 0x78105000 0x0 0x100000>, > + <0x02000000 0x0 0x78205000 0x0 0x78205000 0x0 0x1dfb000>, > + <0x03000000 0x7 0x80000000 0x7 0x80000000 0x0 0x20000000>; Please align the '<'s (in all pcie nodes) > + pcie4_phy: phy@1bf6000 { > + compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; > + reg = <0x0 0x01bf6000 0x0 0x2000>; > + > + clocks = <&gcc GCC_PCIE_PHY_4_AUX_CLK>, > + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, > + <&tcsr TCSR_PCIE_2_CLKREF_EN>, > + <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, > + <&gcc GCC_PCIE_4_PIPE_CLK>, > + <&gcc GCC_PCIE_4_PIPE_DIV2_CLK>; > + clock-names = "aux", > + "cfg_ahb", > + "ref", > + "rchng", > + "pipe", > + "pipediv2"; Please align the '""'s (in all pcie phy nodes) [...] > + interconnects = <&pcie_east_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &pcie_east_slv_noc SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; And the '&s' [...] > + pcie6: pci@1c00000 { > + device_type = "pci"; > + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; > + reg = <0x0 0x01c00000 0x0 0x3000>, > + <0x0 0x7e000000 0x0 0xf20>, > + <0x0 0x7e000f40 0x0 0xa8>, > + <0x0 0x7e001000 0x0 0x4000>, > + <0x0 0x7e100000 0x0 0x100000>, > + <0x0 0x01c03000 0x0 0x1000>; I'm a little confused about the lack of ECAM enablement (through a large config space), but I suppose we'll see that soon.. Konrad