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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from DM4PR12MB6254.namprd12.prod.outlook.com (2603:10b6:8:a5::17) by PH7PR12MB8595.namprd12.prod.outlook.com (2603:10b6:510:1b5::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.615.9; Wed, 11 Nov 2026 10:12:17 +0000 Received: from DM4PR12MB6254.namprd12.prod.outlook.com ([fe80::8211:9b5a:99d2:ffa1]) by DM4PR12MB6254.namprd12.prod.outlook.com ([fe80::8211:9b5a:99d2:ffa1%4]) with mapi id 15.21.0615.007; Wed, 11 Nov 2026 10:12:16 +0000 Message-ID: Date: Wed, 11 Nov 2026 10:12:10 +0000 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v17 12/19] PCI/CXL: Add CXL Device Reset sequencing To: Srirangan Madhavan , Alison Schofield , Bjorn Helgaas , Dave Jiang , Davidlohr Bueso , Ira Weiny , Jonathan Cameron , Vishal Verma , linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Li Ming , Joshua Machauer , Alex Williamson , vsethi@nvidia.com, alwilliamson@nvidia.com, Sai Yashwanth Reddy Kancherla , Vishal Aslot , Manish Honap , Jiandi An , Richard Cheng , linux-tegra@vger.kernel.org References: <20261105185917.2667656-1-smadhavan@nvidia.com> <20261105185917.2667656-13-smadhavan@nvidia.com> Content-Language: en-GB From: "Lucero Palau, Alejandro" In-Reply-To: <20261105185917.2667656-13-smadhavan@nvidia.com> Content-Type: text/plain; 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Wait for the timeout the device > advertises, up to 100 seconds, and access only Status2 until reset > completion, error or expiry, as CXL 4.0 section 9.7.3 requires. Control2 > cleanup runs only afterwards. Treat Control2 command bits as > transient state, restore cache policy on exit, preserve the primary error, > and abort when IOMMU preparation fails. > > Reuse Device DVSEC discovery from cache initialization and keep the > reset entry point declaration private to PCI core. > > Signed-off-by: Srirangan Madhavan Hi Srirangan, A concern regarding IOMMU handling below. If it turns to be unfounded, you can add my review tag. Thank you, Alejandro > +static int __cxl_reset_execute(struct pci_dev *pdev, int dvsec, u16 cap) > +{ > + int rc, rc2; > + > + if (!pci_wait_for_pending_transaction(pdev)) { > + pci_err(pdev, "timed out waiting for pending transactions\n"); > + return -ETIMEDOUT; > + } > + > + rc = pci_dev_reset_iommu_prepare(pdev); I'm not sure if this is safe enough. I can see a situation where a Type2 device could not be using CXL.mem and CXL.cache but CXL.io. This would imply no CXL initialization from the Type2 driver but:     1) Such a driver could be giving functionality without CXL     2) The device belonging to an IOMMU domain which such functionality is using     3) The HDM decoder range as a system resource is free. If I am right, a CXL reset could happen, and although it should not be triggered by user space under these circumstances, the door is open ... The solution would be, currently, to check for a  driver not bound to the device in an IOMMU enabled system. I say currently because CXL.cache will need extra work with IOMMU mapping which are not yet there.