From: Atish Patra <atish.patra@linux.dev>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Alexandre Ghiti <alex@ghiti.fr>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 07/12] RISC-V: KVM: Use ncsr_xyz() in kvm_riscv_vcpu_trap_redirect()
Date: Fri, 13 Jun 2025 17:46:38 -0700 [thread overview]
Message-ID: <f60715b1-3d15-4929-95c6-f21b433c14c5@linux.dev> (raw)
In-Reply-To: <20250613065743.737102-8-apatel@ventanamicro.com>
On 6/12/25 11:57 PM, Anup Patel wrote:
> The H-extension CSRs accessed by kvm_riscv_vcpu_trap_redirect() will
> trap when KVM RISC-V is running as Guest/VM hence remove these traps
> by using ncsr_xyz() instead of csr_xyz().
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/kvm/vcpu_exit.c | 13 +++++++------
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c
> index 6e0c18412795..85c43c83e3b9 100644
> --- a/arch/riscv/kvm/vcpu_exit.c
> +++ b/arch/riscv/kvm/vcpu_exit.c
> @@ -9,6 +9,7 @@
> #include <linux/kvm_host.h>
> #include <asm/csr.h>
> #include <asm/insn-def.h>
> +#include <asm/kvm_nacl.h>
>
> static int gstage_page_fault(struct kvm_vcpu *vcpu, struct kvm_run *run,
> struct kvm_cpu_trap *trap)
> @@ -135,7 +136,7 @@ unsigned long kvm_riscv_vcpu_unpriv_read(struct kvm_vcpu *vcpu,
> void kvm_riscv_vcpu_trap_redirect(struct kvm_vcpu *vcpu,
> struct kvm_cpu_trap *trap)
> {
> - unsigned long vsstatus = csr_read(CSR_VSSTATUS);
> + unsigned long vsstatus = ncsr_read(CSR_VSSTATUS);
>
> /* Change Guest SSTATUS.SPP bit */
> vsstatus &= ~SR_SPP;
> @@ -151,15 +152,15 @@ void kvm_riscv_vcpu_trap_redirect(struct kvm_vcpu *vcpu,
> vsstatus &= ~SR_SIE;
>
> /* Update Guest SSTATUS */
> - csr_write(CSR_VSSTATUS, vsstatus);
> + ncsr_write(CSR_VSSTATUS, vsstatus);
>
> /* Update Guest SCAUSE, STVAL, and SEPC */
> - csr_write(CSR_VSCAUSE, trap->scause);
> - csr_write(CSR_VSTVAL, trap->stval);
> - csr_write(CSR_VSEPC, trap->sepc);
> + ncsr_write(CSR_VSCAUSE, trap->scause);
> + ncsr_write(CSR_VSTVAL, trap->stval);
> + ncsr_write(CSR_VSEPC, trap->sepc);
>
> /* Set Guest PC to Guest exception vector */
> - vcpu->arch.guest_context.sepc = csr_read(CSR_VSTVEC);
> + vcpu->arch.guest_context.sepc = ncsr_read(CSR_VSTVEC);
>
> /* Set Guest privilege mode to supervisor */
> vcpu->arch.guest_context.sstatus |= SR_SPP;
Reviewed-by: Atish Patra <atishp@rivosinc.com>
next prev parent reply other threads:[~2025-06-14 0:47 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-13 6:57 [PATCH v2 00/12] MMU related improvements for KVM RISC-V Anup Patel
2025-06-13 6:57 ` [PATCH v2 01/12] RISC-V: KVM: Check kvm_riscv_vcpu_alloc_vector_context() return value Anup Patel
2025-06-13 6:57 ` [PATCH v2 02/12] RISC-V: KVM: Drop the return value of kvm_riscv_vcpu_aia_init() Anup Patel
2025-06-13 6:57 ` [PATCH v2 03/12] RISC-V: KVM: Rename and move kvm_riscv_local_tlb_sanitize() Anup Patel
2025-06-13 6:57 ` [PATCH v2 04/12] RISC-V: KVM: Replace KVM_REQ_HFENCE_GVMA_VMID_ALL with KVM_REQ_TLB_FLUSH Anup Patel
2025-06-13 6:57 ` [PATCH v2 05/12] RISC-V: KVM: Don't flush TLB when PTE is unchanged Anup Patel
2025-06-14 0:09 ` Atish Patra
2025-06-13 6:57 ` [PATCH v2 06/12] RISC-V: KVM: Implement kvm_arch_flush_remote_tlbs_range() Anup Patel
2025-06-14 0:43 ` Atish Patra
2025-06-17 4:58 ` Anup Patel
2025-06-13 6:57 ` [PATCH v2 07/12] RISC-V: KVM: Use ncsr_xyz() in kvm_riscv_vcpu_trap_redirect() Anup Patel
2025-06-14 0:46 ` Atish Patra [this message]
2025-06-13 6:57 ` [PATCH v2 08/12] RISC-V: KVM: Factor-out MMU related declarations into separate headers Anup Patel
2025-06-18 6:41 ` Atish Patra
2025-06-13 6:57 ` [PATCH v2 09/12] RISC-V: KVM: Introduce struct kvm_gstage_mapping Anup Patel
2025-06-18 7:36 ` Atish Patra
2025-06-13 6:57 ` [PATCH v2 10/12] RISC-V: KVM: Add vmid field to struct kvm_riscv_hfence Anup Patel
2025-06-14 19:29 ` Atish Patra
2025-06-13 6:57 ` [PATCH v2 11/12] RISC-V: KVM: Factor-out g-stage page table management Anup Patel
2025-06-13 6:57 ` [PATCH v2 12/12] RISC-V: KVM: Pass VMID as parameter to kvm_riscv_hfence_xyz() APIs Anup Patel
2025-06-14 19:12 ` Atish Patra
2025-06-14 19:18 ` Atish Patra
2025-06-17 5:11 ` Anup Patel
2025-06-18 6:40 ` Atish Patra
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