From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759999AbcAKQDn (ORCPT ); Mon, 11 Jan 2016 11:03:43 -0500 Received: from sci-ig2.spreadtrum.com ([222.66.158.135]:38886 "EHLO SHSQR01.spreadtrum.com" rhost-flags-OK-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1759831AbcAKQDm (ORCPT ); Mon, 11 Jan 2016 11:03:42 -0500 X-Greylist: delayed 18476 seconds by postgrey-1.27 at vger.kernel.org; Mon, 11 Jan 2016 11:03:41 EST From: =?gb2312?B?Wmhhb3lhbmcgSHVhbmcgKLvGs6/R9Ck=?= To: Catalin Marinas , Lorenzo Pieralisi CC: Zhaoyang Huang , "will.deacon@arm.com" , "linux-kernel@vger.kernel.org" , "hanjun.guo@linaro.org" , "suzuki.poulose@arm.com" , Mark Rutland Subject: RE: [RFC PATCH] Add IPI entry for CPU UP Thread-Topic: [RFC PATCH] Add IPI entry for CPU UP Thread-Index: AQHRTEAZvaAFol2I4U2E6K1NLIRC5571juSAgAACCwCAAJAwJg== Date: Mon, 11 Jan 2016 10:55:08 +0000 Message-ID: References: <1452496240-21060-1-git-send-email-zhaoyang.huang@spreadtrum.com> <20160111095925.GA17852@red-moon>,<20160111100644.GD9554@e104818-lin.cambridge.arm.com> In-Reply-To: <20160111100644.GD9554@e104818-lin.cambridge.arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.0.1.253] Content-Type: text/plain; charset="gb2312" MIME-Version: 1.0 X-MAIL: SHSQR01.spreadtrum.com u0BAt9QR021544 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id u0BG3mRY001163 ________________________________________ From: Catalin Marinas Sent: Monday, January 11, 2016 6:06 PM To: Lorenzo Pieralisi Cc: Zhaoyang Huang; Zhaoyang Huang (»Æ³¯Ñô); will.deacon@arm.com; linux-kernel@vger.kernel.org; hanjun.guo@linaro.org; suzuki.poulose@arm.com; Mark Rutland Subject: Re: [RFC PATCH] Add IPI entry for CPU UP On Mon, Jan 11, 2016 at 09:59:25AM +0000, Lorenzo Pieralisi wrote: > On Mon, Jan 11, 2016 at 03:10:40PM +0800, Zhaoyang Huang wrote: > > In some ARM SOCs, IPI interrupt is used for hotplug in one cpu, that is, > > sending a IPI to the core in WFI and powerdown status. So Add a IPI > > entry for handle this kind of cpu up interrupt > > On arm64 SOCs, with a mainline kernel, you can only hotplug CPUs out > and back in by using the PSCI firmware interface, which does not > require an IPI to boot a CPU, therefore this patch is useless. I fully agree. BTW, such patches should cc linux-arm-kernel@lists.infradead.org as well since they are ARM related. Hi both, In fact, this patch is related to the counterpart of the PSCI code in kernel world which you mentioned before. In SPRD's SOC, we have to implement a way of "wakeup" the core in powerdown state, which is to launch a IPI to the dest core. The reason why we can not accessing power related register to light on the core is the state machine of the PMU will not be safe for this scenario. -- Catalin