From: Andrew Lunn <andrew@lunn.ch>
To: Chris Packham <Chris.Packham@alliedtelesis.co.nz>
Cc: "hkallweit1@gmail.com" <hkallweit1@gmail.com>,
"linux@armlinux.org.uk" <linux@armlinux.org.uk>,
"davem@davemloft.net" <davem@davemloft.net>,
"edumazet@google.com" <edumazet@google.com>,
"kuba@kernel.org" <kuba@kernel.org>,
"pabeni@redhat.com" <pabeni@redhat.com>,
"daniel@makrotopia.org" <daniel@makrotopia.org>,
"markus.stockhausen@gmx.de" <markus.stockhausen@gmx.de>,
"sander@svanheule.net" <sander@svanheule.net>,
netdev <netdev@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v10] net: mdio: Add RTL9300 MDIO driver
Date: Thu, 13 Mar 2025 23:07:55 +0100 [thread overview]
Message-ID: <f6165df5-eedb-4a11-add0-2ae4d4052d6a@lunn.ch> (raw)
In-Reply-To: <6ae8b7c6-8e75-4bfc-9ea3-302269a26951@alliedtelesis.co.nz>
> I'm pretty sure it would upset the hardware polling mechanism which
> unfortunately we can't disable (earlier I thought we could but there are
> various switch features that rely on it).
So we need to get a better understanding of that polling. How are you
telling it about the aquantia PHY features? How does it know it needs
to get the current link rate from MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1
which is a vendor register, not a standard C45 register? How do you
teach it to decode bits in that register?
Andrew
next prev parent reply other threads:[~2025-03-13 22:41 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20250313010726.2181302-1-chris.packham@alliedtelesis.co.nz>
[not found] ` <f7c7f28b-f2b0-464a-a621-d4b2f815d206@lunn.ch>
2025-03-13 19:54 ` Chris Packham
2025-03-13 20:35 ` Andrew Lunn
2025-03-13 20:37 ` Chris Packham
2025-03-13 20:40 ` Andrew Lunn
2025-03-13 20:44 ` Chris Packham
2025-03-13 22:07 ` Andrew Lunn [this message]
2025-03-13 22:53 ` Chris Packham
2025-03-13 23:01 ` Daniel Golle
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