From: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
Vikash Garodia <vikash.garodia@oss.qualcomm.com>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Bryan O'Donoghue <bod@kernel.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 5/8] media: iris: remove duplicateion between generic gen2 data and qcs8300
Date: Thu, 9 Oct 2025 11:40:00 +0530 [thread overview]
Message-ID: <f622da01-3eb3-1aae-f788-d4dc6c22617f@oss.qualcomm.com> (raw)
In-Reply-To: <20251008-iris-sc7280-v1-5-def050ba5e1f@oss.qualcomm.com>
On 10/8/2025 10:03 AM, Dmitry Baryshkov wrote:
> Now as we have removed PIPE value from inst_fw_caps_dec there should be
> no difference between inst_fw_caps of QCS8300 and SM8550+. Drop the
> QCS8300-specific tables and use generic one instead.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> .../media/platform/qcom/iris/iris_platform_gen2.c | 28 +-
> .../platform/qcom/iris/iris_platform_qcs8300.h | 550 ---------------------
> 2 files changed, 18 insertions(+), 560 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> index 7ad03a800356ae9fb73bdbd6d09928d0b500cb3c..5ddc579a73bbc75e3bfca5881d6eee4aa40f09c9 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> @@ -12,7 +12,6 @@
> #include "iris_vpu_buffer.h"
> #include "iris_vpu_common.h"
>
> -#include "iris_platform_qcs8300.h"
> #include "iris_platform_sm8650.h"
> #include "iris_platform_sm8750.h"
>
> @@ -993,11 +992,20 @@ const struct iris_platform_data sm8750_data = {
> .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
> };
>
> -/*
> - * Shares most of SM8550 data except:
> - * - inst_caps to platform_inst_cap_qcs8300
> - * - inst_fw_caps to inst_fw_cap_qcs8300
> - */
> +static struct platform_inst_caps platform_inst_cap_qcs8300 = {
> + .min_frame_width = 96,
> + .max_frame_width = 4096,
> + .min_frame_height = 96,
> + .max_frame_height = 4096,
> + .max_mbpf = (4096 * 2176) / 256,
> + .mb_cycles_vpp = 200,
> + .mb_cycles_fw = 326389,
> + .mb_cycles_fw_vpp = 44156,
> + .num_comv = 0,
> + .max_frame_rate = MAXIMUM_FPS,
> + .max_operating_rate = MAXIMUM_FPS,
> +};
> +
Agree with removing the fw_caps and using the generic ones.
But inst_caps should still be in separate header file for qcs8300, to keep
design consistent across SOCs.
Thanks,
Dikshita
> const struct iris_platform_data qcs8300_data = {
> .get_instance = iris_hfi_gen2_get_instance,
> .init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
> @@ -1022,10 +1030,10 @@ const struct iris_platform_data qcs8300_data = {
> .fwname = "qcom/vpu/vpu30_p4_s6.mbn",
> .pas_id = IRIS_PAS_ID,
> .inst_caps = &platform_inst_cap_qcs8300,
> - .inst_fw_caps_dec = inst_fw_cap_qcs8300_dec,
> - .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_qcs8300_dec),
> - .inst_fw_caps_enc = inst_fw_cap_qcs8300_enc,
> - .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_qcs8300_enc),
> + .inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
> + .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
> + .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
> + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
> .tz_cp_config_data = &tz_cp_config_sm8550,
> .core_arch = VIDEO_ARCH_LX,
> .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
> deleted file mode 100644
> index 612526a938eed0554fc0da99e12c26d22e04bb6e..0000000000000000000000000000000000000000
> --- a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
> +++ /dev/null
> @@ -1,550 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
> - */
> -
> -#define BITRATE_MAX 245000000
> -
> -static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] = {
> - {
> - .cap_id = PROFILE_H264,
> - .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> - .max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
> - .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
> - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
> - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
> - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) |
> - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH),
> - .value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
> - .hfi_id = HFI_PROP_PROFILE,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> - .set = iris_set_u32_enum,
> - },
> - {
> - .cap_id = PROFILE_HEVC,
> - .min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> - .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE,
> - .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE),
> - .value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> - .hfi_id = HFI_PROP_PROFILE,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> - .set = iris_set_u32_enum,
> - },
> - {
> - .cap_id = PROFILE_VP9,
> - .min = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
> - .max = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
> - .step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0) |
> - BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_2),
> - .value = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
> - .hfi_id = HFI_PROP_PROFILE,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> - .set = iris_set_u32_enum,
> - },
> - {
> - .cap_id = LEVEL_H264,
> - .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
> - .max = V4L2_MPEG_VIDEO_H264_LEVEL_6_2,
> - .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_1) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_2),
> - .value = V4L2_MPEG_VIDEO_H264_LEVEL_6_1,
> - .hfi_id = HFI_PROP_LEVEL,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> - .set = iris_set_u32_enum,
> - },
> - {
> - .cap_id = LEVEL_HEVC,
> - .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
> - .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2,
> - .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2),
> - .value = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1,
> - .hfi_id = HFI_PROP_LEVEL,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> - .set = iris_set_u32_enum,
> - },
> - {
> - .cap_id = LEVEL_VP9,
> - .min = V4L2_MPEG_VIDEO_VP9_LEVEL_1_0,
> - .max = V4L2_MPEG_VIDEO_VP9_LEVEL_6_0,
> - .step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) |
> - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) |
> - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) |
> - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) |
> - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) |
> - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) |
> - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) |
> - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) |
> - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0) |
> - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_1) |
> - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_2) |
> - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_6_0),
> - .value = V4L2_MPEG_VIDEO_VP9_LEVEL_6_0,
> - .hfi_id = HFI_PROP_LEVEL,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> - .set = iris_set_u32_enum,
> - },
> - {
> - .cap_id = TIER,
> - .min = V4L2_MPEG_VIDEO_HEVC_TIER_MAIN,
> - .max = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
> - .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH),
> - .value = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
> - .hfi_id = HFI_PROP_TIER,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> - .set = iris_set_u32_enum,
> - },
> - {
> - .cap_id = INPUT_BUF_HOST_MAX_COUNT,
> - .min = DEFAULT_MAX_HOST_BUF_COUNT,
> - .max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
> - .step_or_mask = 1,
> - .value = DEFAULT_MAX_HOST_BUF_COUNT,
> - .hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
> - .flags = CAP_FLAG_INPUT_PORT,
> - .set = iris_set_u32,
> - },
> - {
> - .cap_id = STAGE,
> - .min = STAGE_1,
> - .max = STAGE_2,
> - .step_or_mask = 1,
> - .value = STAGE_2,
> - .hfi_id = HFI_PROP_STAGE,
> - .set = iris_set_stage,
> - },
> - {
> - .cap_id = PIPE,
> - .min = PIPE_1,
> - /* .max is set via platform data */
> - .step_or_mask = 1,
> - /* .value is set via platform data */
> - .hfi_id = HFI_PROP_PIPE,
> - .set = iris_set_pipe,
> - },
> - {
> - .cap_id = POC,
> - .min = 0,
> - .max = 2,
> - .step_or_mask = 1,
> - .value = 1,
> - .hfi_id = HFI_PROP_PIC_ORDER_CNT_TYPE,
> - },
> - {
> - .cap_id = CODED_FRAMES,
> - .min = CODED_FRAMES_PROGRESSIVE,
> - .max = CODED_FRAMES_PROGRESSIVE,
> - .step_or_mask = 0,
> - .value = CODED_FRAMES_PROGRESSIVE,
> - .hfi_id = HFI_PROP_CODED_FRAMES,
> - },
> - {
> - .cap_id = BIT_DEPTH,
> - .min = BIT_DEPTH_8,
> - .max = BIT_DEPTH_8,
> - .step_or_mask = 1,
> - .value = BIT_DEPTH_8,
> - .hfi_id = HFI_PROP_LUMA_CHROMA_BIT_DEPTH,
> - },
> - {
> - .cap_id = RAP_FRAME,
> - .min = 0,
> - .max = 1,
> - .step_or_mask = 1,
> - .value = 1,
> - .hfi_id = HFI_PROP_DEC_START_FROM_RAP_FRAME,
> - .flags = CAP_FLAG_INPUT_PORT,
> - .set = iris_set_u32,
> - },
> -};
> -
> -static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_enc[] = {
> - {
> - .cap_id = PROFILE_H264,
> - .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> - .max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
> - .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
> - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) |
> - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
> - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
> - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH),
> - .value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
> - .hfi_id = HFI_PROP_PROFILE,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> - },
> - {
> - .cap_id = PROFILE_HEVC,
> - .min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> - .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
> - .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10),
> - .value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> - .hfi_id = HFI_PROP_PROFILE,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> - },
> - {
> - .cap_id = LEVEL_H264,
> - .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
> - .max = V4L2_MPEG_VIDEO_H264_LEVEL_6_0,
> - .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) |
> - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0),
> - .value = V4L2_MPEG_VIDEO_H264_LEVEL_5_0,
> - .hfi_id = HFI_PROP_LEVEL,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> - },
> - {
> - .cap_id = LEVEL_HEVC,
> - .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
> - .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2,
> - .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) |
> - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2),
> - .value = V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
> - .hfi_id = HFI_PROP_LEVEL,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> - },
> - {
> - .cap_id = STAGE,
> - .min = STAGE_1,
> - .max = STAGE_2,
> - .step_or_mask = 1,
> - .value = STAGE_2,
> - .hfi_id = HFI_PROP_STAGE,
> - },
> - {
> - .cap_id = HEADER_MODE,
> - .min = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
> - .max = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
> - .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) |
> - BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME),
> - .value = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
> - .hfi_id = HFI_PROP_SEQ_HEADER_MODE,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> - },
> - {
> - .cap_id = PREPEND_SPSPPS_TO_IDR,
> - .min = 0,
> - .max = 1,
> - .step_or_mask = 1,
> - .value = 0,
> - },
> - {
> - .cap_id = BITRATE,
> - .min = 1,
> - .max = BITRATE_MAX,
> - .step_or_mask = 1,
> - .value = BITRATE_DEFAULT,
> - .hfi_id = HFI_PROP_TOTAL_BITRATE,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> - CAP_FLAG_DYNAMIC_ALLOWED,
> - },
> - {
> - .cap_id = BITRATE_PEAK,
> - .min = 1,
> - .max = BITRATE_MAX,
> - .step_or_mask = 1,
> - .value = BITRATE_DEFAULT,
> - .hfi_id = HFI_PROP_TOTAL_PEAK_BITRATE,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> - CAP_FLAG_DYNAMIC_ALLOWED,
> - },
> - {
> - .cap_id = BITRATE_MODE,
> - .min = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
> - .max = V4L2_MPEG_VIDEO_BITRATE_MODE_CBR,
> - .step_or_mask = BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) |
> - BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR),
> - .value = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
> - .hfi_id = HFI_PROP_RATE_CONTROL,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> - },
> - {
> - .cap_id = FRAME_SKIP_MODE,
> - .min = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
> - .max = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT,
> - .step_or_mask = BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) |
> - BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT) |
> - BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT),
> - .value = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> - },
> - {
> - .cap_id = FRAME_RC_ENABLE,
> - .min = 0,
> - .max = 1,
> - .step_or_mask = 1,
> - .value = 1,
> - },
> - {
> - .cap_id = GOP_SIZE,
> - .min = 0,
> - .max = INT_MAX,
> - .step_or_mask = 1,
> - .value = 2 * DEFAULT_FPS - 1,
> - .hfi_id = HFI_PROP_MAX_GOP_FRAMES,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> - CAP_FLAG_DYNAMIC_ALLOWED,
> - },
> - {
> - .cap_id = ENTROPY_MODE,
> - .min = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
> - .max = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
> - .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) |
> - BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC),
> - .value = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
> - .hfi_id = HFI_PROP_CABAC_SESSION,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> - },
> - {
> - .cap_id = MIN_FRAME_QP_H264,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = MIN_QP_8BIT,
> - .hfi_id = HFI_PROP_MIN_QP_PACKED,
> - .flags = CAP_FLAG_OUTPUT_PORT,
> - },
> - {
> - .cap_id = MIN_FRAME_QP_HEVC,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = MIN_QP_8BIT,
> - .hfi_id = HFI_PROP_MIN_QP_PACKED,
> - .flags = CAP_FLAG_OUTPUT_PORT,
> - },
> - {
> - .cap_id = MAX_FRAME_QP_H264,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = MAX_QP,
> - .hfi_id = HFI_PROP_MAX_QP_PACKED,
> - .flags = CAP_FLAG_OUTPUT_PORT,
> - },
> - {
> - .cap_id = MAX_FRAME_QP_HEVC,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = MAX_QP,
> - .hfi_id = HFI_PROP_MAX_QP_PACKED,
> - .flags = CAP_FLAG_OUTPUT_PORT,
> - },
> - {
> - .cap_id = I_FRAME_MIN_QP_H264,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = MIN_QP_8BIT,
> - },
> - {
> - .cap_id = I_FRAME_MIN_QP_HEVC,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = MIN_QP_8BIT,
> - },
> - {
> - .cap_id = P_FRAME_MIN_QP_H264,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = MIN_QP_8BIT,
> - },
> - {
> - .cap_id = P_FRAME_MIN_QP_HEVC,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = MIN_QP_8BIT,
> - },
> - {
> - .cap_id = B_FRAME_MIN_QP_H264,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = MIN_QP_8BIT,
> - },
> - {
> - .cap_id = B_FRAME_MIN_QP_HEVC,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = MIN_QP_8BIT,
> - },
> - {
> - .cap_id = I_FRAME_MAX_QP_H264,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = MAX_QP,
> - },
> - {
> - .cap_id = I_FRAME_MAX_QP_HEVC,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = MAX_QP,
> - },
> - {
> - .cap_id = P_FRAME_MAX_QP_H264,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = MAX_QP,
> - },
> - {
> - .cap_id = P_FRAME_MAX_QP_HEVC,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = MAX_QP,
> - },
> - {
> - .cap_id = B_FRAME_MAX_QP_H264,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = MAX_QP,
> - },
> - {
> - .cap_id = B_FRAME_MAX_QP_HEVC,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = MAX_QP,
> - },
> - {
> - .cap_id = I_FRAME_QP_H264,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = DEFAULT_QP,
> - .hfi_id = HFI_PROP_QP_PACKED,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> - CAP_FLAG_DYNAMIC_ALLOWED,
> - },
> - {
> - .cap_id = I_FRAME_QP_HEVC,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = DEFAULT_QP,
> - .hfi_id = HFI_PROP_QP_PACKED,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> - CAP_FLAG_DYNAMIC_ALLOWED,
> - },
> - {
> - .cap_id = P_FRAME_QP_H264,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = DEFAULT_QP,
> - .hfi_id = HFI_PROP_QP_PACKED,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> - CAP_FLAG_DYNAMIC_ALLOWED,
> - },
> - {
> - .cap_id = P_FRAME_QP_HEVC,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = DEFAULT_QP,
> - .hfi_id = HFI_PROP_QP_PACKED,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> - CAP_FLAG_DYNAMIC_ALLOWED,
> - },
> - {
> - .cap_id = B_FRAME_QP_H264,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = DEFAULT_QP,
> - .hfi_id = HFI_PROP_QP_PACKED,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> - CAP_FLAG_DYNAMIC_ALLOWED,
> - },
> - {
> - .cap_id = B_FRAME_QP_HEVC,
> - .min = MIN_QP_8BIT,
> - .max = MAX_QP,
> - .step_or_mask = 1,
> - .value = DEFAULT_QP,
> - .hfi_id = HFI_PROP_QP_PACKED,
> - .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> - CAP_FLAG_DYNAMIC_ALLOWED,
> - },
> -};
> -
> -static struct platform_inst_caps platform_inst_cap_qcs8300 = {
> - .min_frame_width = 96,
> - .max_frame_width = 4096,
> - .min_frame_height = 96,
> - .max_frame_height = 4096,
> - .max_mbpf = (4096 * 2176) / 256,
> - .mb_cycles_vpp = 200,
> - .mb_cycles_fw = 326389,
> - .mb_cycles_fw_vpp = 44156,
> - .num_comv = 0,
> - .max_frame_rate = MAXIMUM_FPS,
> - .max_operating_rate = MAXIMUM_FPS,
> -};
>
next prev parent reply other threads:[~2025-10-09 6:10 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-08 4:32 [PATCH 0/8] media: iris: port support for Qualcomm SC7280 Dmitry Baryshkov
2025-10-08 4:32 ` [PATCH 1/8] media: iris: turn platform caps into constants Dmitry Baryshkov
2025-10-08 8:32 ` Bryan O'Donoghue
2025-10-09 6:08 ` Dikshita Agarwal
2025-10-09 14:45 ` Dmitry Baryshkov
2025-10-08 4:33 ` [PATCH 2/8] media: iris: turn platform data " Dmitry Baryshkov
2025-10-08 8:32 ` Bryan O'Donoghue
2025-10-09 6:09 ` Dikshita Agarwal
2025-10-08 4:33 ` [PATCH 3/8] media: iris: stop copying r/o data Dmitry Baryshkov
2025-10-08 23:48 ` Bryan O'Donoghue
2025-10-09 0:16 ` Dmitry Baryshkov
2025-10-08 4:33 ` [PATCH 4/8] media: iris: stop encoding PIPE value into fw_caps Dmitry Baryshkov
2025-10-08 8:03 ` Konrad Dybcio
2025-10-08 19:10 ` Dmitry Baryshkov
2025-10-08 4:33 ` [PATCH 5/8] media: iris: remove duplicateion between generic gen2 data and qcs8300 Dmitry Baryshkov
2025-10-08 8:07 ` Konrad Dybcio
2025-10-08 19:15 ` Dmitry Baryshkov
2025-10-09 6:10 ` Dikshita Agarwal [this message]
2025-10-09 14:46 ` Dmitry Baryshkov
2025-10-08 4:33 ` [PATCH 6/8] media: iris: rename sm8250 platform file to gen1 Dmitry Baryshkov
2025-10-08 8:08 ` Konrad Dybcio
2025-10-09 7:50 ` Dikshita Agarwal
2025-10-08 4:33 ` [PATCH 7/8] media: iris: move common register definitions to the header Dmitry Baryshkov
2025-10-08 23:50 ` Bryan O'Donoghue
2025-10-09 6:10 ` Dikshita Agarwal
2025-10-09 14:48 ` Dmitry Baryshkov
2025-10-14 9:13 ` Vikash Garodia
2025-10-14 9:51 ` Dmitry Baryshkov
2025-10-14 10:10 ` Vikash Garodia
2025-10-08 4:33 ` [PATCH 8/8] media: iris: enable support for SC7280 platform Dmitry Baryshkov
2025-10-08 8:26 ` Konrad Dybcio
2025-10-08 19:25 ` Dmitry Baryshkov
2025-10-09 9:19 ` Konrad Dybcio
2025-10-09 15:00 ` Dmitry Baryshkov
2025-10-09 15:49 ` Konrad Dybcio
2025-10-09 16:20 ` Dmitry Baryshkov
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