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Thu, 23 Oct 2025 16:03:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE+gtW3iL5YfktBLtM22DaFOWiosZsm9piWaW0gD11XXUYwJYStL7NWGN9b5nOT3GQP6iSqfA== X-Received: by 2002:a17:903:244b:b0:290:9a31:26da with SMTP id d9443c01a7336-290c9d31109mr329081175ad.16.1761260617079; Thu, 23 Oct 2025 16:03:37 -0700 (PDT) Received: from [192.168.1.5] ([106.222.232.102]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2946de0c927sm35158665ad.46.2025.10.23.16.03.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 Oct 2025 16:03:36 -0700 (PDT) Message-ID: Date: Fri, 24 Oct 2025 04:33:28 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/6] dt-bindings: display/msm/gmu: Document A612 RGMU To: Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson References: <20251017-qcs615-spin-2-v1-0-0baa44f80905@oss.qualcomm.com> <20251017-qcs615-spin-2-v1-3-0baa44f80905@oss.qualcomm.com> <8f3f4874-2e82-473e-87bd-e3bd58089b90@kernel.org> <181af756-09a1-4694-98c4-53cea556e172@oss.qualcomm.com> Content-Language: en-US From: Akhil P Oommen In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE4MDAxNSBTYWx0ZWRfXy1zSHhnOTcyK 9xiBMt5a5x1E6Iq4pQCsLQx/VZD4ob62RNZVIyj13MtI5RzCpPPlpX1q0JGYZpvBxk80/ZJ5XQg 5BZo9igsgNXhE8osf/lz5/tq2dL/zd8eiLpHfP3tjU52ZzjcoBti+86QRTCHtlT2jT3cloAmLE6 HzKg32bVjS+kESvrA1fDORN+aJ6KJuGmY4Vn9tOJnspFlKrGJ6E4evwZWMojnkpSGkqyhdfWjpW mwvv9lnHQrNfSZaaTJKU42OOmsn4QTRNxr1CBdPtJ9N7HbBk7JkCt71GsJi9w7Hc8Hx/AzZAWfR /8jZhTMZgM0KVrEW5fSDdGbxV950GJ5IMyEPoB/oMma6bYBEmo4zQ9W1DpuTwRykTpQ8BT7ybmG r65vT8DnW9YvlrXZOHAJbX+mN/wAwQ== X-Authority-Analysis: v=2.4 cv=bNUb4f+Z c=1 sm=1 tr=0 ts=68fab44b cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=OORdEvYNKPdDRPFHMUl15A==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=Oc1YgfMCT3OOBMc9zysA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: 9HnbBRbihY8YxEq0Il7V3m_-WdeVAFpr X-Proofpoint-ORIG-GUID: 9HnbBRbihY8YxEq0Il7V3m_-WdeVAFpr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-23_03,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 adultscore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510180015 On 10/22/2025 12:49 AM, Krzysztof Kozlowski wrote: > On 21/10/2025 17:51, Akhil P Oommen wrote: >> On 10/19/2025 2:43 PM, Krzysztof Kozlowski wrote: >>> On 17/10/2025 19:08, Akhil P Oommen wrote: >>>> RGMU a.k.a Reduced Graphics Management Unit is a small state machine >>>> with the sole purpose of providing IFPC (Inter Frame Power Collapse) >>>> support. Compared to GMU, it doesn't manage GPU clock, voltage >>>> scaling, bw voting or any other functionalities. All it does is detect >>>> an idle GPU and toggle the GDSC switch. As it doesn't access DDR space, >>>> it doesn't require iommu. >>>> >>>> So far, only Adreno 612 GPU has an RGMU core. Document RGMU in the GMU's >>>> schema. >>>> >>>> Signed-off-by: Akhil P Oommen >>>> --- >>>> .../devicetree/bindings/display/msm/gmu.yaml | 98 +++++++++++++++++----- >>>> 1 file changed, 79 insertions(+), 19 deletions(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml >>>> index afc1879357440c137cadeb2d9a74ae8459570a25..a262d41755f09f21f607bf7a1fd567f386595f39 100644 >>>> --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml >>>> +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml >>>> @@ -26,6 +26,9 @@ properties: >>>> - items: >>>> - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$' >>>> - const: qcom,adreno-gmu >>>> + - items: >>>> + - const: qcom,adreno-rgmu-612.0 >>>> + - const: qcom,adreno-rgmu >>>> - const: qcom,adreno-gmu-wrapper >>>> >>>> reg: >>>> @@ -45,24 +48,30 @@ properties: >>>> maxItems: 7 >>>> >>>> interrupts: >>>> - items: >>>> - - description: GMU HFI interrupt >>>> - - description: GMU interrupt >>> >>> >>> Both stay, just explain what is the first interrupt. You should not drop >>> descriptions here. Look at every other binding - of course except that >>> terrible Adreno GPU which is anti-example. >> >> Do you mean we should use a OneOf and list both combo? Or elaborate the >> description of the first interrupt to include OOB too? Something like: >> >> - description: HFI interrupt on GMU and OOB interrupt on RGMU. > > Yes, like that. > >> >> Sorry, I am a bit confused. >> >>> >>>> + minItems: 2 >>>> + maxItems: 2 >>>> >>>> interrupt-names: >>>> - items: >>>> - - const: hfi >>>> - - const: gmu >>>> + oneOf: >>>> + - items: >>>> + - const: hfi >>>> + description: GMU HFI interrupt >>> >>> No, descriptions never go to xxx-names, but to xxx. >>> >>>> + - const: gmu >>>> + description: GMU interrupt >>>> + - items: >>>> + - const: oob >>>> + description: GMU OOB interrupt >>>> + - const: gmu >>>> + description: GMU interrupt >>>> + >>>> >>>> power-domains: >>>> - items: >>>> - - description: CX power domain >>>> - - description: GX power domain >>>> + minItems: 2 >>>> + maxItems: 3 >>> >>> No. >> I will keep the 'description'. Here, RGMU has 3 power domains instead of >> 2. I suppose we should add the description for the 3rd power domain here >> and keep 'minItems: 2' property to override the default 3? > > Yes. > >> >>> >>>> >>>> power-domain-names: >>>> - items: >>>> - - const: cx >>>> - - const: gx >>>> + minItems: 2 >>>> + maxItems: 3 >>> >>> >>> No. Why? >> Same as above. >> >>> >>>> >>>> iommus: >>>> maxItems: 1 >>>> @@ -86,6 +95,44 @@ required: >>>> additionalProperties: false >>>> >>>> allOf: >>>> + - if: >>>> + properties: >>>> + compatible: >>>> + contains: >>>> + const: qcom,adreno-rgmu-612.0 >>>> + then: >>>> + properties: >>>> + reg: >>>> + items: >>>> + - description: Core RGMU registers >>>> + reg-names: >>>> + items: >>>> + - const: gmu >>>> + clocks: >>>> + items: >>>> + - description: GMU clock >>>> + - description: GPU CX clock >>>> + - description: GPU AXI clock >>>> + - description: GPU MEMNOC clock >>>> + - description: GPU SMMU vote clock >>>> + clock-names: >>>> + items: >>>> + - const: gmu >>>> + - const: cxo >>>> + - const: axi >>>> + - const: memnoc >>>> + - const: smmu_vote >>>> + power-domains: >>>> + items: >>>> + - description: CX power domain >>>> + - description: GX power domain >>>> + - description: VDD_CX power domain >>>> + power-domain-names: >>>> + items: >>>> + - const: cx >>>> + - const: gx >>>> + - const: vdd_cx >>> >>> This does not make even sense. Why did you remove the the common list >>> from power-domain-names? >>> >>>> + >>>> - if: >>>> properties: >>>> compatible: >>>> @@ -313,13 +360,26 @@ allOf: >>>> items: >>>> - const: gmu >>>> else: >>>> - required: >>>> - - clocks >>>> - - clock-names >>>> - - interrupts >>>> - - interrupt-names >>>> - - iommus >>>> - - operating-points-v2 >>>> + if: >>>> + properties: >>>> + compatible: >>>> + contains: >>>> + const: qcom,adreno-rgmu >>>> + then: >>>> + required: >>>> + - clocks >>>> + - clock-names >>>> + - interrupts >>>> + - interrupt-names >>>> + - operating-points-v2 >>>> + else: >>> >>> No. Don't nest multiple ifs. >> >> I guess we should split this. I will add a 'required' constraint to the >> rgmu constraints above. And apply the below 'required' constraint >> specifically to 'qcom,adreno-gmu' instead of the 'else' fallback case. >> >> Please let me know if you have any suggestion. > > Maybe the binding is getting to complicated and RGMU should have its own. There is just a single chipset with RGMU and we haven't seen another one in the last 8 yrs. So it is very unlikely we will see another one again. So I feel it is not worth splitting this file just for RGMU. Let me send another revision and let's take a call after that. -Akhil. > > > Best regards, > Krzysztof