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Subject: Re: [PATCH 0/5] Use mmio-sram driver for Keystone MSMC RAM
To: Santosh Shilimkar <santosh.shilimkar@oracle.com>,
        Santosh Shilimkar <ssantosh@kernel.org>
References: <20160901225846.31058-1-s-anna@ti.com>
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CC: Russell King <linux@armlinux.org.uk>, Rob Herring <robh+dt@kernel.org>,
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        Vitaly Andrianov <vitalya@ti.com>
From: Suman Anna <s-anna@ti.com>
Message-ID: <f6920801-554d-18e8-f140-44aeeb2f878e@ti.com>
Date: Wed, 7 Sep 2016 11:22:02 -0500
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Hi Santosh,

On 09/07/2016 11:11 AM, Santosh Shilimkar wrote:
> Hi Suman,
> 
> On 9/1/2016 3:58 PM, Suman Anna wrote:
>> Hi,
>>
>> The Keystone 2 family of SoCs have an on-chip RAM called the
>> Multicore Shared Memory (MSM) RAM. This RAM is accessible through
>> the Multicore Shared Memory Controller (MSMC). This series represents
>> these on-chip RAMs as sram nodes so that the memory allocations
>> can be managed by the in-kernel mmio-sram driver.
>>
>> The first 4 patches adds the basic SRAM nodes on each of the SoCs,
>> and the last patch enables the generic on-chip SRAM driver for
>> keystone defconfig.
>>
> The series looks good in general but I would like to understand
> the users of this memory in kernel. Is that going to be posted
> as a follow up patch ? Is the Power controller going to make
> use of this SRAM for PM code ?

Yes, the users will eventually follow. Power Controller code is not
gonna be using this SRAM, it has its own RAM. This memory is gonna be
split between various functional features like IPC, OPTEE integration,
we already have the Boot Monitor code using this. We will have the
memory split by either having static child nodes or drivers requesting
the memory using gen_pool API.

regards
Suman