From: Yegor Yefremov <yegorslists@googlemail.com>
To: David Woodhouse <dwmw2@infradead.org>
Cc: linux-kernel@vger.kernel.org
Subject: Re: Add support for the SST 39VF3202, 39VF6401B and 39VF6402B flash chips
Date: Thu, 25 Jun 2009 10:47:33 +0200 [thread overview]
Message-ID: <f69abfc30906250147n7e0b2945x50af858f52adb904@mail.gmail.com> (raw)
In-Reply-To: <1245917167.17089.102.camel@macbook.infradead.org>
>> Add support for the SST 39VF3202, 39VF6401B and 39VF6402B flash chips
>>
>> - extend struct amd_flash_info to enable 8 erase regions for 8Mb flash chips
>
> If you didn't mean 8,000,000 bits, don't say it. Did you mean 8MiB?
Sure I mean 8MiB
>> - change erase block command to 0x50 due to the differences between
>> 39VF6401/02 and 39VF6401B/02B chips
>
> Hm, can you elucidate?
Please refer to the data sheets Table 6:
39VF6401B data sheet http://www.sst.com/downloads/datasheet/S71288.pdf
39VF6401 data sheet http://www.sst.com/downloads/datasheet/S71223-03.pdf
The difference in the 6th bus write cycle. 39VF6401B uses 0x50 and
39VF6401 uses 0x30.
> And should that be done as a quirk instead?
How should I do it? The commend is not a part of any structure. Can we
add such a field to the struct amd_flash_info describing erase
sequence?
Yegor
next prev parent reply other threads:[~2009-06-25 8:47 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-06-25 7:42 Yegor Yefremov
2009-06-25 8:06 ` David Woodhouse
2009-06-25 8:47 ` Yegor Yefremov [this message]
2009-06-29 7:42 ` Yegor Yefremov
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