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[75.142.250.213]) by smtp.gmail.com with ESMTPSA id d46sm2548270qtk.37.2020.08.05.09.02.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 05 Aug 2020 09:02:12 -0700 (PDT) Subject: Re: [PATCH 5/6] include: fpga: adi-axi-common.h: add definitions for supported FPGAs To: Alexandru Ardelean , linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, mdf@kernel.org, Mircea Caprioru References: <20200804110658.40911-1-alexandru.ardelean@analog.com> <20200804110658.40911-6-alexandru.ardelean@analog.com> From: Tom Rix Message-ID: Date: Wed, 5 Aug 2020 09:02:10 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <20200804110658.40911-6-alexandru.ardelean@analog.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/4/20 4:06 AM, Alexandru Ardelean wrote: > From: Mircea Caprioru > > All (newer) FPGA IP cores supported by Analog Devices, store information in > the synthesized designs. This information describes various parameters, > including the family of boards on which this is deployed, speed-grade, and > so on. > > Currently, some of these definitions are deployed mostly on Xilinx boards, > but they have been considered also for FPGA boards from other vendors. > > The register definitions are described at this link: > https://wiki.analog.com/resources/fpga/docs/hdl/regmap > (the 'Base (common to all cores)' section). > > Signed-off-by: Mircea Caprioru > Signed-off-by: Alexandru Ardelean > --- > include/linux/fpga/adi-axi-common.h | 37 +++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/include/linux/fpga/adi-axi-common.h b/include/linux/fpga/adi-axi-common.h > index 141ac3f251e6..7cca2d62cc45 100644 > --- a/include/linux/fpga/adi-axi-common.h > +++ b/include/linux/fpga/adi-axi-common.h > @@ -13,6 +13,9 @@ > > #define ADI_AXI_REG_VERSION 0x0000 > > +#define ADI_AXI_REG_FPGA_INFO 0x001C > +#define ADI_AXI_REG_FPGA_VOLTAGE 0x0140 > + > #define ADI_AXI_PCORE_VER(major, minor, patch) \ > (((major) << 16) | ((minor) << 8) | (patch)) > > @@ -20,4 +23,38 @@ > #define ADI_AXI_PCORE_VER_MINOR(version) (((version) >> 8) & 0xff) > #define ADI_AXI_PCORE_VER_PATCH(version) ((version) & 0xff) > > +#define ADI_AXI_INFO_FPGA_VOLTAGE(val) ((val) & 0xffff) > + > +#define ADI_AXI_INFO_FPGA_TECH(info) (((info) >> 24) & 0xff) > +#define ADI_AXI_INFO_FPGA_FAMILY(info) (((info) >> 16) & 0xff) > +#define ADI_AXI_INFO_FPGA_SPEED_GRADE(info) (((info) >> 8) & 0xff) > + > +enum adi_axi_fgpa_technology { enum types are defined but not used.  It would be better to convert all of these to #defines. These are only the Xilinx values. Need to add the Intel values from https://github.com/analogdevicesinc/hdl/blob/master/library/scripts/adi_intel_device_info_enc.tcl The #define names need to include XILINX or INTEL. Tom > + ADI_AXI_FPGA_TECH_UNKNOWN = 0, > + ADI_AXI_FPGA_TECH_SERIES7, > + ADI_AXI_FPGA_TECH_ULTRASCALE, > + ADI_AXI_FPGA_TECH_ULTRASCALE_PLUS, > +}; > + > +enum adi_axi_fpga_family { > + ADI_AXI_FPGA_FAMILY_UNKNOWN = 0, > + ADI_AXI_FPGA_FAMILY_ARTIX, > + ADI_AXI_FPGA_FAMILY_KINTEX, > + ADI_AXI_FPGA_FAMILY_VIRTEX, > + ADI_AXI_FPGA_FAMILY_ZYNQ, > +}; > + > +enum adi_axi_fpga_speed_grade { > + ADI_AXI_FPGA_SPEED_UNKNOWN = 0, > + ADI_AXI_FPGA_SPEED_1 = 10, > + ADI_AXI_FPGA_SPEED_1L = 11, > + ADI_AXI_FPGA_SPEED_1H = 12, > + ADI_AXI_FPGA_SPEED_1HV = 13, > + ADI_AXI_FPGA_SPEED_1LV = 14, > + ADI_AXI_FPGA_SPEED_2 = 20, > + ADI_AXI_FPGA_SPEED_2L = 21, > + ADI_AXI_FPGA_SPEED_2LV = 22, > + ADI_AXI_FPGA_SPEED_3 = 30, > +}; > + > #endif /* ADI_AXI_COMMON_H_ */