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From: Hrushikesh Salunke <h-salunke@ti.com>
To: Vignesh Raghavendra <vigneshr@ti.com>, <nm@ti.com>,
	<kristo@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,
	<conor+dt@kernel.org>
Cc: <s-vadapalli@ti.com>, <linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<danishanwar@ti.com>, Hrushikesh Salunke <h-salunke@ti.com>
Subject: Re: [PATCH v2] arm64: dts: ti: k3-am642-evm-pcie0-ep: Add boot phase tag to "pcie0_ep"
Date: Thu, 12 Jun 2025 15:46:50 +0530	[thread overview]
Message-ID: <f6a57a82-c534-4439-a337-8592c2e121c5@ti.com> (raw)
In-Reply-To: <b24a97fc-8dac-443b-aec7-317b9e393f2d@ti.com>



On 11/06/25 14:17, Hrushikesh Salunke wrote:
> 
> 
> On 11/06/25 14:14, Vignesh Raghavendra wrote:
>>
>>
>> On 10/06/25 11:19, Hrushikesh Salunke wrote:
>>> AM64X SoC has one instance of PCIe which is PCIe0. To support PCIe boot
>>> on AM64X SoC, PCIe0 needs to be in endpoint mode and it needs to be
>>> functional at all stages of PCIe boot process. Thus add the
>>> "bootph-all" boot phase tag to "pcie0_ep" device tree node.
>>>
>>> Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
>>> ---
>>> This patch is based on commit
>>> 475c850a7fdd Add linux-next specific files for 20250606
>>>
>>> Changes since v1
>>> As per feedback from Nishanth, changed the position of "bootph-all"
>>> tag, according to ordering rules for device tree properties.
>>>
>>> v1 : 
>>> https://lore.kernel.org/all/20250609115930.w2s6jzg7xii55dlu@speckled/
>>>
>>>   arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso | 1 +
>>>   1 file changed, 1 insertion(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso 
>>> b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
>>> index 432751774853..a7e8d4ea98ac 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
>>> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
>>> @@ -46,6 +46,7 @@ pcie0_ep: pcie-ep@f102000 {
>>>           max-functions = /bits/ 8 <1>;
>>>           phys = <&serdes0_pcie_link>;
>>>           phy-names = "pcie-phy";
>>> +        bootph-all;
>>>           ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
>>>       };
>>>   };
>>
>> Are the patches for PCIe boot support merged to U-Boot or such other
>> bootloader repo?
>> No, they are not in the U-Boot yet. I will be posting patches for PCIe
> boot support for U-Boot this week.
> 

I have posted Patch series for the PCIe boot support in Uboot.

1.https://patchwork.ozlabs.org/project/uboot/patch/20250612084910.3457060-1-h-salunke@ti.com/
2. 
https://patchwork.ozlabs.org/project/uboot/cover/20250612085023.3457117-1-h-salunke@ti.com/
3. 
https://patchwork.ozlabs.org/project/uboot/cover/20250612085534.3457522-1-h-salunke@ti.com/


Regards,
Hrushikesh.

  reply	other threads:[~2025-06-12 10:17 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-10  5:49 Hrushikesh Salunke
2025-06-10  5:51 ` Siddharth Vadapalli
2025-06-11  8:44 ` Vignesh Raghavendra
2025-06-11  8:47   ` Hrushikesh Salunke
2025-06-12 10:16     ` Hrushikesh Salunke [this message]
2025-06-19  7:55       ` Vignesh Raghavendra
2025-06-19  8:33         ` Hrushikesh Salunke
2025-06-26  4:03 ` Vignesh Raghavendra

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