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Wed, 28 Jan 2026 21:30:32 -0800 (PST) X-Received: by 2002:a17:90b:2f04:b0:340:ad5e:cb with SMTP id 98e67ed59e1d1-353fecdcfabmr6603840a91.8.1769664632180; Wed, 28 Jan 2026 21:30:32 -0800 (PST) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3540f2cb0a7sm4092295a91.2.2026.01.28.21.30.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Jan 2026 21:30:31 -0800 (PST) Message-ID: Date: Thu, 29 Jan 2026 11:00:26 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] PCI: dwc: Use common D3cold eligibility helper in suspend path To: Bjorn Andersson Cc: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Will Deacon , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jonathanh@nvidia.com References: <20260128-d3cold-v1-0-dd8f3f0ce824@oss.qualcomm.com> <20260128-d3cold-v1-2-dd8f3f0ce824@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=PfvyRyhd c=1 sm=1 tr=0 ts=697af079 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=nF4YfsMlPaNBOkUFFLkA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: pPyM5Fmhz7oVvNjP5KBHfNxlmeHjr_Y_ X-Proofpoint-ORIG-GUID: pPyM5Fmhz7oVvNjP5KBHfNxlmeHjr_Y_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI5MDAzMyBTYWx0ZWRfX40rjv5Q2s4Ie Epx/R2c+wMxeU5QGlJDmPaJ+NDpABxt1RAe/HzFxLO9cFsKqtVkilub3CkQOPYeIokOeWFFOoCF rhNmD/Ig/qpE7wuRmpX6UthCIVWRL9Xc7H5BO1xqxjTILjyzCfm6MdCPddJr7v/WhwgAhwz6/Ph wZ4RwexwGLNgmJvcfcuyyhDHhIdiofmfWXwPfhhaamimvGZKX2GLBaqJM+JuyQP7dRfZ2h3Ij9U 13qynxm9gFqm0kTwLkX4DsDZi7681yRWsqxcLTnyJ2qQKD0vAvwXVxGDEzArBir6tT+nNwq6k10 +L/PrrD1WZCd2T+hmb1mR5ZTukbzr+GN+6+dQ/E51GivFq4tJ7GMVGxszKr2ku5BprLfL3TU0/u c4z0wrhP7dkH0QO9KrLPn8h07N6u3PvBAgZUacRFVVChARfietbF5+zj4SBJQje1Vg3uABcZX9d e73FTIgS6Kgj4nM1f/A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-28_06,2026-01-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 spamscore=0 malwarescore=0 adultscore=0 clxscore=1015 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601290033 On 1/28/2026 7:58 PM, Bjorn Andersson wrote: > On Wed, Jan 28, 2026 at 05:10:42PM +0530, Krishna Chaitanya Chundru wrote: >> Previously, the driver skipped putting the link into L2/device state in >> D3cold whenever L1 ASPM was enabled, since some devices (e.g. NVMe) expect >> low resume latency and may not tolerate deeper power states. However, such >> devices typically remain in D0 and are already covered by the new helper's >> requirement that all endpoints be in D3hot before the host bridge may >> enter D3cold. >> >> So, replace the local L1/L1SS-based check in dw_pcie_suspend_noirq() with >> the shared pci_host_common_can_enter_d3cold() helper to decide whether the >> DesignWare host bridge can safely transition to D3cold. >> >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> drivers/pci/controller/dwc/pcie-designware-host.c | 7 +------ >> drivers/pci/controller/dwc/pcie-designware.h | 1 + >> 2 files changed, 2 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c >> index 372207c33a857b4c98572bb1e9b61fa0080bc871..2c8056761addf7febc1b0e06ddf8ba4dd4ad1684 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware-host.c >> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c >> @@ -1157,15 +1157,10 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) >> >> int dw_pcie_suspend_noirq(struct dw_pcie *pci) >> { >> - u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); >> u32 val; >> int ret; >> >> - /* >> - * If L1SS is supported, then do not put the link into L2 as some >> - * devices such as NVMe expect low resume latency. >> - */ >> - if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1) >> + if (!pci_host_common_can_enter_d3cold(pci->pp.bridge)) >> return 0; >> >> if (pci->pp.ops->pme_turn_off) { >> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h >> index 31685951a080456b8834aab2bf79a36c78f46639..18d8f7d5d23088b2fa177e84a21d900c98850fcd 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware.h >> +++ b/drivers/pci/controller/dwc/pcie-designware.h >> @@ -26,6 +26,7 @@ >> #include >> #include >> >> +#include "../pci-host-common.h" > Why doesn't this include go in the c file? I don't see that all c files Ack, will do this in v2. - Krishna Chaitanya. > including pcie-designware.h now needs this. > > Regards, > Bjorn > >> #include "../../pci.h" >> >> /* DWC PCIe IP-core versions (native support since v4.70a) */ >> >> -- >> 2.34.1 >> >>