From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FAA923815D; Wed, 30 Apr 2025 13:14:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746018865; cv=none; b=dXRgrI/t5KV+yMWDVD7Ba8DE25VIEWvGk9Q9oRoYsO0WQfuDESaiOfemITIa5/0VEXVpuBojBMXlmiGhC7SF10DgVl/glmUgVnfjoRnQfdUv5hAnOhZSwEzaeB8Lc8TNx8vxZe3CF+jYi++yrfKuagaIxC0RLZhfGZuHTz28a2o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746018865; c=relaxed/simple; bh=4K229jTSEoytrVRGZYVTEIZe34wrIcvfDmHAIE9mKeA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=NoqIuC6g13Ojsxy6Uqu21uAPTcBBgU+Wg78oZbJw24XUs73d4k4PC6Fm8250TEY9KsGqrPyfTcxgqpMxa+pVZ996BNSVcLbrSukx4tECwd+rtHz8vnbX6OYlkZsEFzqvwyf37sbFjdzGa1JJ6ug3wzwS4s2lv15xIbWOg4h++yE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=JW4AOmsG; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="JW4AOmsG" Received: from [192.168.88.20] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id D372F725; Wed, 30 Apr 2025 15:14:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1746018853; bh=4K229jTSEoytrVRGZYVTEIZe34wrIcvfDmHAIE9mKeA=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=JW4AOmsG6Kn/ZVRKTcOkxxuHthEJOaYEnAorz2LDD0JwH3iPbO8CZgsDeuVNHsZQB U6Rfc6hjDP7BVbTDrkNb81fhjh0sAs65tTs5XcTcq2ZEiDxC0jSsINxUs85qno5x+1 vQQqJzyHM++a9LMioqC7AaItR5Z9Mmcxm1mDXtOY= Message-ID: Date: Wed, 30 Apr 2025 16:14:15 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/3] drm/tidss: Update infrastructure to support K3 DSS cut-down versions To: Devarsh Thakkar Cc: praneeth@ti.com, vigneshr@ti.com, aradhya.bhatia@linux.dev, s-jain1@ti.com, r-donadkar@ti.com, j-choudhary@ti.com, h-shenoy@ti.com, jyri.sarha@iki.fi, airlied@gmail.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, dri-devel@lists.freedesktop.org, simona@ffwll.ch, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org References: <20250429143656.3252877-1-devarsht@ti.com> <20250429143656.3252877-3-devarsht@ti.com> Content-Language: en-US From: Tomi Valkeinen Autocrypt: addr=tomi.valkeinen@ideasonboard.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi, On 29/04/2025 17:36, Devarsh Thakkar wrote: > SoCs like AM62Lx support cut-down version of K3 DSS where although same > register space is supported as in other K3 DSS supported SoCs such as > AM65x, AM62x, AM62Ax but some of the resources such as planes and > corresponding register spaces are truncated. > > For e.g. AM62Lx has only single VIDL pipeline supported, so corresponding > register spaces for other video pipelines need to be skipped. > > To add a generic support for future SoCs where one or more video pipelines > can get truncated from the parent register space, move the video plane > related information to vid_info struct which will also have a field to > indicate hardware index of each of the available video planes, so that > driver only maps and programs those video pipes and skips the unavailable > ones. > > While at it, also change the num_planes field in the features structure to > num_vid so that all places in code which use vid_info structure are > highlighted in the code. > > Signed-off-by: Devarsh Thakkar > --- > V5: > - Use separate variable for hw_id and add it in missing places to access > correct VID pipeline bits in common registers > > V4: > - Create vid_info struct only for instantiated planes > - s/num_planes/num_vids > - s/vid_lite/is_lite > - Add hw_id member in vid_info struct and remove is_present > > V2->V3: > - No change (patch introduced in V3) > > drivers/gpu/drm/tidss/tidss_crtc.c | 11 +- > drivers/gpu/drm/tidss/tidss_dispc.c | 152 +++++++++++++++++++++------- > drivers/gpu/drm/tidss/tidss_dispc.h | 11 +- > drivers/gpu/drm/tidss/tidss_kms.c | 2 +- > drivers/gpu/drm/tidss/tidss_plane.c | 2 +- > 5 files changed, 131 insertions(+), 47 deletions(-) > > diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tidss_crtc.c > index 94f8e3178df5..c555f6717e7d 100644 > --- a/drivers/gpu/drm/tidss/tidss_crtc.c > +++ b/drivers/gpu/drm/tidss/tidss_crtc.c > @@ -130,7 +130,7 @@ static void tidss_crtc_position_planes(struct tidss_device *tidss, > !to_tidss_crtc_state(cstate)->plane_pos_changed) > return; > > - for (layer = 0; layer < tidss->feat->num_planes; layer++) { > + for (layer = 0; layer < tidss->feat->num_vids ; layer++) { > struct drm_plane_state *pstate; > struct drm_plane *plane; > bool layer_active = false; > @@ -271,9 +271,12 @@ static void tidss_crtc_atomic_disable(struct drm_crtc *crtc, > * another videoport, the DSS will report sync lost issues. Disable all > * the layers here as a work-around. > */ > - for (u32 layer = 0; layer < tidss->feat->num_planes; layer++) > - dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport, layer, > - false); > + for (u32 layer = 0; layer < tidss->feat->num_vids; layer++) { > + u32 hw_id = tidss->feat->vid_info[layer].hw_id; > + > + dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport, > + hw_id, false); > + } > > dispc_vp_disable(tidss->dispc, tcrtc->hw_videoport); > > diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c > index cacb5f3d8085..da6fe4e3ca85 100644 > --- a/drivers/gpu/drm/tidss/tidss_dispc.c > +++ b/drivers/gpu/drm/tidss/tidss_dispc.c > @@ -103,9 +103,16 @@ const struct dispc_features dispc_k2g_feats = { > }, > }, > > - .num_planes = 1, > - .vid_name = { "vid1" }, > - .vid_lite = { false }, > + .num_vids = 1, > + > + .vid_info = { > + { > + .name = "vid1", > + .is_lite = false, > + .hw_id = 0, > + }, > + }, > + > .vid_order = { 0 }, > }; > > @@ -178,11 +185,22 @@ const struct dispc_features dispc_am65x_feats = { > }, > }, > > - .num_planes = 2, > + .num_vids = 2, > /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ > - .vid_name = { "vid", "vidl1" }, > - .vid_lite = { false, true, }, > - .vid_order = { 1, 0 }, > + .vid_info = { > + { > + .name = "vid", > + .is_lite = false, > + .hw_id = 0, > + }, > + { > + .name = "vidl1", > + .is_lite = true, > + .hw_id = 1, > + }, > + }, > + > + .vid_order = {1, 0}, > }; > > static const u16 tidss_j721e_common_regs[DISPC_COMMON_REG_TABLE_LEN] = { > @@ -267,9 +285,32 @@ const struct dispc_features dispc_j721e_feats = { > .gamma_type = TIDSS_GAMMA_10BIT, > }, > }, > - .num_planes = 4, > - .vid_name = { "vid1", "vidl1", "vid2", "vidl2" }, > - .vid_lite = { 0, 1, 0, 1, }, > + > + .num_vids = 4, > + > + .vid_info = { > + { > + .name = "vid1", > + .is_lite = false, > + .hw_id = 0, > + }, > + { > + .name = "vidl1", > + .is_lite = true, > + .hw_id = 1, > + }, > + { > + .name = "vid2", > + .is_lite = false, > + .hw_id = 2, > + }, > + { > + .name = "vidl2", > + .is_lite = true, > + .hw_id = 3, > + }, > + }, > + > .vid_order = { 1, 3, 0, 2 }, > }; > > @@ -315,11 +356,23 @@ const struct dispc_features dispc_am625_feats = { > }, > }, > > - .num_planes = 2, > + .num_vids = 2, > + > /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ > - .vid_name = { "vid", "vidl1" }, > - .vid_lite = { false, true, }, > - .vid_order = { 1, 0 }, > + .vid_info = { > + { > + .name = "vid", > + .is_lite = false, > + .hw_id = 0, > + }, > + { > + .name = "vidl1", > + .is_lite = true, > + .hw_id = 1, > + } > + }, > + > + .vid_order = {1, 0}, > }; > > const struct dispc_features dispc_am62a7_feats = { > @@ -369,11 +422,22 @@ const struct dispc_features dispc_am62a7_feats = { > }, > }, > > - .num_planes = 2, > - /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ > - .vid_name = { "vid", "vidl1" }, > - .vid_lite = { false, true, }, > - .vid_order = { 1, 0 }, > + .num_vids = 2, > + > + .vid_info = { > + { > + .name = "vid", > + .is_lite = false, > + .hw_id = 0, > + }, > + { > + .name = "vidl1", > + .is_lite = true, > + .hw_id = 1, > + } > + }, > + > + .vid_order = {1, 0}, > }; > > static const u16 *dispc_common_regmap; > @@ -788,9 +852,12 @@ void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask) > if (clearmask & DSS_IRQ_VP_MASK(i)) > dispc_k3_vp_write_irqstatus(dispc, i, clearmask); > } > - for (i = 0; i < dispc->feat->num_planes; ++i) { > + > + for (i = 0; i < dispc->feat->num_vids; ++i) { > + u32 hw_id = dispc->feat->vid_info[i].hw_id; > + > if (clearmask & DSS_IRQ_PLANE_MASK(i)) > - dispc_k3_vid_write_irqstatus(dispc, i, clearmask); > + dispc_k3_vid_write_irqstatus(dispc, hw_id, clearmask); > } > > /* always clear the top level irqstatus */ > @@ -809,8 +876,11 @@ dispc_irq_t dispc_k3_read_and_clear_irqstatus(struct dispc_device *dispc) > for (i = 0; i < dispc->feat->num_vps; ++i) > status |= dispc_k3_vp_read_irqstatus(dispc, i); > > - for (i = 0; i < dispc->feat->num_planes; ++i) > - status |= dispc_k3_vid_read_irqstatus(dispc, i); > + for (i = 0; i < dispc->feat->num_vids; ++i) { > + u32 hw_id = dispc->feat->vid_info[i].hw_id; > + > + status |= dispc_k3_vid_read_irqstatus(dispc, hw_id); > + } > > dispc_k3_clear_irqstatus(dispc, status); > > @@ -825,8 +895,11 @@ static dispc_irq_t dispc_k3_read_irqenable(struct dispc_device *dispc) > for (i = 0; i < dispc->feat->num_vps; ++i) > enable |= dispc_k3_vp_read_irqenable(dispc, i); > > - for (i = 0; i < dispc->feat->num_planes; ++i) > - enable |= dispc_k3_vid_read_irqenable(dispc, i); > + for (i = 0; i < dispc->feat->num_vids; ++i) { > + u32 hw_id = dispc->feat->vid_info[i].hw_id; > + > + enable |= dispc_k3_vid_read_irqenable(dispc, hw_id); > + } > > return enable; > } > @@ -849,19 +922,22 @@ static void dispc_k3_set_irqenable(struct dispc_device *dispc, > main_enable |= BIT(i); /* VP IRQ */ > else > main_disable |= BIT(i); /* VP IRQ */ > + > } > > - for (i = 0; i < dispc->feat->num_planes; ++i) { > - dispc_k3_vid_set_irqenable(dispc, i, mask); > + for (i = 0; i < dispc->feat->num_vids; ++i) { > + u32 hw_id = dispc->feat->vid_info[i].hw_id; > + > + dispc_k3_vid_set_irqenable(dispc, hw_id, mask); > + > if (mask & DSS_IRQ_PLANE_MASK(i)) > - main_enable |= BIT(i + 4); /* VID IRQ */ > + main_enable |= BIT(hw_id + 4); /* VID IRQ */ > else > - main_disable |= BIT(i + 4); /* VID IRQ */ > + main_disable |= BIT(hw_id + 4); /* VID IRQ */ > } > > if (main_enable) > dispc_write(dispc, DISPC_IRQENABLE_SET, main_enable); > - > if (main_disable) > dispc_write(dispc, DISPC_IRQENABLE_CLR, main_disable); > > @@ -2025,7 +2101,7 @@ int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane, > const struct drm_plane_state *state, > u32 hw_videoport) > { > - bool lite = dispc->feat->vid_lite[hw_plane]; > + bool lite = dispc->feat->vid_info[hw_plane].is_lite; I don't think this is correct. You can't access the vid_info[] with the hw-id. > u32 fourcc = state->fb->format->format; > bool need_scaling = state->src_w >> 16 != state->crtc_w || > state->src_h >> 16 != state->crtc_h; > @@ -2096,7 +2172,7 @@ void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane, > const struct drm_plane_state *state, > u32 hw_videoport) > { > - bool lite = dispc->feat->vid_lite[hw_plane]; > + bool lite = dispc->feat->vid_info[hw_plane].is_lite; Here too. > u32 fourcc = state->fb->format->format; > u16 cpp = state->fb->format->cpp[0]; > u32 fb_width = state->fb->pitches[0] / cpp; > @@ -2210,7 +2286,7 @@ static void dispc_k2g_plane_init(struct dispc_device *dispc) > /* MFLAG_START = MFLAGNORMALSTARTMODE */ > REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); > > - for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { > + for (hw_plane = 0; hw_plane < dispc->feat->num_vids; hw_plane++) { > u32 size = dispc_vid_get_fifo_size(dispc, hw_plane); > u32 thr_low, thr_high; > u32 mflag_low, mflag_high; > @@ -2226,7 +2302,7 @@ static void dispc_k2g_plane_init(struct dispc_device *dispc) > > dev_dbg(dispc->dev, > "%s: bufsize %u, buf_threshold %u/%u, mflag threshold %u/%u preload %u\n", > - dispc->feat->vid_name[hw_plane], > + dispc->feat->vid_info[hw_plane].name, Here hw_plane is not actually the hw-id (anymore), but elsewhere in this function it is used as a hw-id, which is no longer correct. > size, > thr_high, thr_low, > mflag_high, mflag_low, > @@ -2265,7 +2341,7 @@ static void dispc_k3_plane_init(struct dispc_device *dispc) > /* MFLAG_START = MFLAGNORMALSTARTMODE */ > REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); > > - for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { > + for (hw_plane = 0; hw_plane < dispc->feat->num_vids; hw_plane++) { > u32 size = dispc_vid_get_fifo_size(dispc, hw_plane); > u32 thr_low, thr_high; > u32 mflag_low, mflag_high; > @@ -2281,7 +2357,7 @@ static void dispc_k3_plane_init(struct dispc_device *dispc) > > dev_dbg(dispc->dev, > "%s: bufsize %u, buf_threshold %u/%u, mflag threshold %u/%u preload %u\n", > - dispc->feat->vid_name[hw_plane], > + dispc->feat->vid_info[hw_plane].name, And here. All these issues make me wonder whether we have the right model. It's just too easy to get the usage wrong. I'm not sure which way to go here. Fix the current issues? It's a bit cumbersome to go from hw-id to the index (needs a search), just to get some hw properties. Or go back to the earlier one, with a vid array containing unused slots? That makes the for loops a bit harder. I need to think about it... Tomi > size, > thr_high, thr_low, > mflag_high, mflag_low, > @@ -2898,8 +2974,8 @@ int dispc_init(struct tidss_device *tidss) > if (r) > return r; > > - for (i = 0; i < dispc->feat->num_planes; i++) { > - r = dispc_iomap_resource(pdev, dispc->feat->vid_name[i], > + for (i = 0; i < dispc->feat->num_vids; i++) { > + r = dispc_iomap_resource(pdev, dispc->feat->vid_info[i].name, > &dispc->base_vid[i]); > if (r) > return r; > diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h > index 086327d51a90..72a0146e57d5 100644 > --- a/drivers/gpu/drm/tidss/tidss_dispc.h > +++ b/drivers/gpu/drm/tidss/tidss_dispc.h > @@ -46,6 +46,12 @@ struct dispc_features_scaling { > u32 xinc_max; > }; > > +struct dispc_vid_info { > + const char *name; /* Should match dt reg names */ > + u32 hw_id; > + bool is_lite; > +}; > + > struct dispc_errata { > bool i2000; /* DSS Does Not Support YUV Pixel Data Formats */ > }; > @@ -82,9 +88,8 @@ struct dispc_features { > const char *vpclk_name[TIDSS_MAX_PORTS]; /* Should match dt clk names */ > const enum dispc_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS]; > struct tidss_vp_feat vp_feat; > - u32 num_planes; > - const char *vid_name[TIDSS_MAX_PLANES]; /* Should match dt reg names */ > - bool vid_lite[TIDSS_MAX_PLANES]; > + u32 num_vids; > + struct dispc_vid_info vid_info[TIDSS_MAX_PLANES]; > u32 vid_order[TIDSS_MAX_PLANES]; > }; > > diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tidss_kms.c > index f371518f8697..19432c08ec6b 100644 > --- a/drivers/gpu/drm/tidss/tidss_kms.c > +++ b/drivers/gpu/drm/tidss/tidss_kms.c > @@ -115,7 +115,7 @@ static int tidss_dispc_modeset_init(struct tidss_device *tidss) > > const struct dispc_features *feat = tidss->feat; > u32 max_vps = feat->num_vps; > - u32 max_planes = feat->num_planes; > + u32 max_planes = feat->num_vids; > > struct pipe pipes[TIDSS_MAX_PORTS]; > u32 num_pipes = 0; > diff --git a/drivers/gpu/drm/tidss/tidss_plane.c b/drivers/gpu/drm/tidss/tidss_plane.c > index 719412e6c346..142ae81951a0 100644 > --- a/drivers/gpu/drm/tidss/tidss_plane.c > +++ b/drivers/gpu/drm/tidss/tidss_plane.c > @@ -200,7 +200,7 @@ struct tidss_plane *tidss_plane_create(struct tidss_device *tidss, > struct tidss_plane *tplane; > enum drm_plane_type type; > u32 possible_crtcs; > - u32 num_planes = tidss->feat->num_planes; > + u32 num_planes = tidss->feat->num_vids; > u32 color_encodings = (BIT(DRM_COLOR_YCBCR_BT601) | > BIT(DRM_COLOR_YCBCR_BT709)); > u32 color_ranges = (BIT(DRM_COLOR_YCBCR_FULL_RANGE) |