Re: [PATCH RESEND v3 0/5] MediaTek PLL Refactors and Fixes

[AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>]

Il 15/12/25 11:23, Nicolas Frattaroli ha scritto:
> This series refactors all users of mtk-pll, just so we can enable
> runtime power management for the clock controllers that want it. It's
> also generally more useful to have the struct device in the pll code,
> rather than the device node.
> 
> Also fix up MT8196 mfgpll to declare its parent-child relationship with
> mfg_eb, and fix the common clock framework core to take
> CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.
> 
> The reason why this is all in the same series is that it grew out of me
> first modelling this as an RPM clock for mfgpll, which Angelo disagreed
> with, so I did some investigation and it seems MFG_EB indeed is a parent
> clock. However, the earlier refactoring to pass the device pointer down
> is still useful.
> 
> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>

Whole series is

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
> Changes in v3:
> - Make device_node forward declaration a device forward declaration
> - Remove forward declarations of struct clk_ops and struct
>    clk_hw_onecell_data. (clk-provider.h include remains as it's needed
>    for a complete type of clk_hw)
> - Move PLL_PARENT_EN flag to individual mfgpll definitions.
> - Link to v2: https://lore.kernel.org/r/20251008-mtk-pll-rpm-v2-0-170ed0698560@collabora.com
> 
> Changes in v2:
> - Drop bindings patch
> - Drop mfgpll RPM patch
> - Add patch to also transition pllfh to passing device
> - Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
>    recalc_rate operation
> - Remodel mfgpll's mfg_eb dependency as parent-child with
>    CLK_OPS_PARENT_ENABLE
> - Link to v1: https://lore.kernel.org/r/20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com
> 
> ---
> Nicolas Frattaroli (5):
>        clk: Respect CLK_OPS_PARENT_ENABLE during recalc
>        clk: mediatek: Refactor pll registration to pass device
>        clk: mediatek: Pass device to clk_hw_register for PLLs
>        clk: mediatek: Refactor pllfh registration to pass device
>        clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
> 
>   drivers/clk/clk.c                            | 13 +++++++++++++
>   drivers/clk/mediatek/clk-mt2701.c            |  2 +-
>   drivers/clk/mediatek/clk-mt2712-apmixedsys.c |  2 +-
>   drivers/clk/mediatek/clk-mt6735-apmixedsys.c |  4 ++--
>   drivers/clk/mediatek/clk-mt6765.c            |  2 +-
>   drivers/clk/mediatek/clk-mt6779.c            |  2 +-
>   drivers/clk/mediatek/clk-mt6795-apmixedsys.c |  2 +-
>   drivers/clk/mediatek/clk-mt6797.c            |  2 +-
>   drivers/clk/mediatek/clk-mt7622-apmixedsys.c |  2 +-
>   drivers/clk/mediatek/clk-mt7629.c            |  2 +-
>   drivers/clk/mediatek/clk-mt7981-apmixed.c    |  2 +-
>   drivers/clk/mediatek/clk-mt7986-apmixed.c    |  2 +-
>   drivers/clk/mediatek/clk-mt7988-apmixed.c    |  2 +-
>   drivers/clk/mediatek/clk-mt8135-apmixedsys.c |  3 ++-
>   drivers/clk/mediatek/clk-mt8167-apmixedsys.c |  2 +-
>   drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
>   drivers/clk/mediatek/clk-mt8183-apmixedsys.c |  2 +-
>   drivers/clk/mediatek/clk-mt8186-apmixedsys.c |  2 +-
>   drivers/clk/mediatek/clk-mt8188-apmixedsys.c |  2 +-
>   drivers/clk/mediatek/clk-mt8192-apmixedsys.c |  2 +-
>   drivers/clk/mediatek/clk-mt8195-apmixedsys.c |  2 +-
>   drivers/clk/mediatek/clk-mt8195-apusys_pll.c |  3 ++-
>   drivers/clk/mediatek/clk-mt8196-apmixedsys.c |  3 ++-
>   drivers/clk/mediatek/clk-mt8196-mcu.c        |  2 +-
>   drivers/clk/mediatek/clk-mt8196-mfg.c        | 15 ++++++++-------
>   drivers/clk/mediatek/clk-mt8196-vlpckgen.c   |  2 +-
>   drivers/clk/mediatek/clk-mt8365-apmixedsys.c |  2 +-
>   drivers/clk/mediatek/clk-mt8516-apmixedsys.c |  2 +-
>   drivers/clk/mediatek/clk-pll.c               | 19 +++++++++++++------
>   drivers/clk/mediatek/clk-pll.h               | 15 ++++++++-------
>   drivers/clk/mediatek/clk-pllfh.c             | 13 ++++++++-----
>   drivers/clk/mediatek/clk-pllfh.h             |  2 +-
>   32 files changed, 87 insertions(+), 59 deletions(-)
> ---
> base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
> change-id: 20250929-mtk-pll-rpm-bf28192dd016
> 
> Best regards,