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Thu, 20 Jun 2024 23:18:03 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGC3Ek3Uc/wSB68KwIgzf9gYnnocy1y8MxT1dU06xNYyZzA1wwesXNJUaTfwWdM/Q2bRttI8w== X-Received: by 2002:a05:6808:3091:b0:3d5:11bd:154c with SMTP id 5614622812f47-3d51b98f9a7mr8803271b6e.2.1718950683174; Thu, 20 Jun 2024 23:18:03 -0700 (PDT) Received: from [10.72.116.78] ([43.228.180.230]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7065119428fsm640113b3a.72.2024.06.20.23.17.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 20 Jun 2024 23:18:02 -0700 (PDT) Message-ID: Date: Fri, 21 Jun 2024 14:17:57 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] KVM: arm64: Allow userspace to change ID_AA64PFR1_EL1 To: Marc Zyngier Cc: Oliver Upton , kvmarm@lists.linux.dev, James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20240618063808.1040085-1-shahuang@redhat.com> <20240618063808.1040085-2-shahuang@redhat.com> <86ed8uk8cr.wl-maz@kernel.org> Content-Language: en-US From: Shaoqin Huang In-Reply-To: <86ed8uk8cr.wl-maz@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Marc, On 6/18/24 15:39, Marc Zyngier wrote: > On Tue, 18 Jun 2024 07:38:06 +0100, > Shaoqin Huang wrote: >> >> Allow userspace to change the guest-visible value of the register with >> some severe limitation: >> >> - No changes to features not virtualized by KVM (MPAM_frac, RAS_frac) >> --- >> arch/arm64/kvm/sys_regs.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c >> index 22b45a15d068..bead81867bce 100644 >> --- a/arch/arm64/kvm/sys_regs.c >> +++ b/arch/arm64/kvm/sys_regs.c >> @@ -2306,7 +2306,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { >> ID_AA64PFR0_EL1_GIC | >> ID_AA64PFR0_EL1_AdvSIMD | >> ID_AA64PFR0_EL1_FP), }, >> - ID_SANITISED(ID_AA64PFR1_EL1), >> + ID_WRITABLE(ID_AA64PFR1_EL1, ~(ID_AA64PFR1_EL1_RAS_frac | >> + ID_AA64PFR1_EL1_MPAM_frac)), >> ID_UNALLOCATED(4,2), >> ID_UNALLOCATED(4,3), >> ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), > > This isn't a valid patch. > > Furthermore, how about all the other features that may or may not be > currently handled by KVM? Please see [1] and make sure that all > existing fields have a known behaviour (a combination of masked, > preserved, capped, writable or read-only). > > I can at least see problems with MTE_frac and MTEX, plus all the other > things that KVM doesn't know how to save/restore (THE, GCS, NMI...). > > What I asked you to handle the whole register, I really meant it. I currently only found the BT and SSBS fields can be written without any unknown behavior. All other fields in the ID_AA64PFR1_EL1 are either not supported by KVM or the field involved with other register and KVM don't know how to handle them. I'm not sure if this is right. So I want to ask about your opinion about how to allow each of the field to be writable in the ID_AA64PFR1_EL1 register? Thanks, Shaoqin > > M. > > [1] https://developer.arm.com/documentation/ddi0601/2024-03/AArch64-Registers/ID-AA64PFR1-EL1--AArch64-Processor-Feature-Register-1?lang=en > -- Shaoqin