From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751618AbZECE0X (ORCPT ); Sun, 3 May 2009 00:26:23 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1750924AbZECE0I (ORCPT ); Sun, 3 May 2009 00:26:08 -0400 Received: from yw-out-2324.google.com ([74.125.46.28]:56011 "EHLO yw-out-2324.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750875AbZECE0G convert rfc822-to-8bit (ORCPT ); Sun, 3 May 2009 00:26:06 -0400 MIME-Version: 1.0 In-Reply-To: References: <625fc13d0904200529l152b8d75g33c3f940de1b2920@mail.gmail.com> <1240388476.17445.10.camel@pasglop> <1241126291.29501.41.camel@pasglop> Date: Sun, 3 May 2009 00:26:05 -0400 Message-ID: Subject: Re: Porting the ibm_newemac driver to use phylib (and other PHY/MAC questions) From: Kyle Moffett To: Benjamin Herrenschmidt Cc: Josh Boyer , netdev , "Linux-Kernel@Vger. Kernel. Org" , linuxppc-dev@ozlabs.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 30, 2009 at 6:21 PM, Kyle Moffett wrote: >>> I'm also curious about the intent of the "mdio_instance" pointer (IE: >>> the "mdio-device" property).  Is that used when all the PHY devices >>> are attached to the MDIO bus of only one of the (multiple) emac >>> devices? >> >> It's common especially on older SoCs using EMAC to have only one of >> the EMAC instance with an MDIO bus for configuring the PHYs. This is one >> of the reasons why I have the mutex in the low level MDIO access >> routines since 2 EMACs can try to talk to the same MDIO, and this is the >> problem I had with phylib back then which was doing everything in atomic >> contexts. > > Ok, good, the current mdiobus code seems to make handling this a good > deal easier. Ok, I've dug through the docs on the 460EPx (the CPU I'm using), and I'd like some confirmation of the following: * The EMAC hardware itself internally has its own dedicated MDIO/MDClk lines, driven by the STACR register. * On many/most cpus, there is only a single set of external MDIO/MDClk pins, driven either off the ZMII bridge or the RGMII bridge. * Both bridge-types have their own internal register for switching the external MDIO/MDClk pins between the two sets of internal EMAC<=>bridge links. * Some SoCs have both an ZMII and an RGMII bridge, and the external MDIO/MDClk pins are only connected to one of the two bridges (How do I know which one? Alternatively, do I just program both and hope for the best?). * Some older SoCs simply export the MDIO/MDClk pins from one of their internal EMAC chips and don't bother with running it through the multiplexing bridge. Are there any SoCs which actually export the MDIO/MDClk pins from both/all of their EMACs? Cheers, Kyle Moffett