From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1009731CA4E for ; Fri, 7 Aug 2026 14:22:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786112551; cv=none; b=JGlMCJuTXjrBd7uBmFub52tYCQu5vEEsCja3gLIC9Qj8HORZVoyBah4XtcmT9ErRMz5DstNGm/t+I6ErryUsU/msU1P85pcsG8ENns/OVhWVvWXh+50OkDGTQ9nIqnbhtCYcJ8i3yyKAVJ18+1tfUWZspK58VV9PasS8i5wf04M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786112551; c=relaxed/simple; bh=Z18AD3eJbmG6g7iT3gQzh9p4HXJKnEXyBQpiwqBYGh8=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=QbpFXsrZhk6+4IWLPtSdpkaEfe3l6W/VfGU/uNC2VHXfSHeAuq2pjUDDuuwH1jLWxHguBFx21gMcylHKgPzKq5b2M/+jCWpjtI3A6QIrCs8FHQQPdChrBXCg6RTdy9K8CVvjiRlZ2KOghGfKyIfGsSXJLEeBdB+mUWE5Hn4J7Ww= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=i8mAA1aR; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="i8mAA1aR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1786112547; bh=Z18AD3eJbmG6g7iT3gQzh9p4HXJKnEXyBQpiwqBYGh8=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=i8mAA1aRBHR+bFJ2R7K3C/2aHumZlngtjHzPJpTITfLHpTtaYspdj00rm/CX2oqKs Aqjj6l9ascZ5trGek5YqHEbIg6zXuk4pLKKATcvCevADfAqDqEVVk43Mt3immfqZbj vIOeLHQx5Y4OAnPgxnNIj9GDZ2RHySE6nPPP7Pckfr9pM41C59JVIqfbQP2ayHPtbL Y6ZZ+tDxO4+ulSQdr8cXKZNWHhFm+qTC/QD/9rkZ62hBVMSZDE5KpUIUuzi2OK56NX ep5fZRTPXJalm+l+PmqDOlmU8rqWPYDo6XlI6UX/oSRpzJncgyyhRkkNE8QZrAzkq6 BBf9pYRKvDrvQ== Received: from [100.64.0.241] (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange x25519) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 6A53517E021C; Fri, 07 Aug 2026 16:22:27 +0200 (CEST) Message-ID: Date: Fri, 7 Aug 2026 17:22:27 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 05/10] phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes To: Manivannan Sadhasivam Cc: Vinod Koul , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov , kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?Q?Thomas_Niederpr=C3=BCm?= , Simon Wright , Diederik de Haas , Andy Yan References: <20260723-hdptx-clk-fixes-v5-0-8e786067865f@collabora.com> <20260723-hdptx-clk-fixes-v5-5-8e786067865f@collabora.com> Content-Language: en-US From: Cristian Ciocaltea In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 8/7/26 4:04 PM, Manivannan Sadhasivam wrote: > On Thu, Jul 23, 2026 at 10:41:48PM +0300, Cristian Ciocaltea wrote: >> Any changes to the PHY link rate and/or color depth done via the HDMI >> PHY configuration API are not immediately programmed into the hardware, >> but are delayed until the PHY usage count gets incremented from 0 to 1, >> that is when it is powered on or when the PLL clock exposed through >> the CCF API is prepared, whichever comes first. >> >> Since the clock might remain in prepared state after subsequent PHY >> config changes, the programming can also be triggered via >> clk_ops.set_rate(). However, from the clock consumer perspective (i.e. >> VOP2 display controller), the (pixel) clock rate doesn't vary with bpc, >> as that is handled internally by the PHY and reflected in the TDMS >> character rate only. >> >> As a consequence, changing the bpc while preserving the modeline may >> lead to out-of-sync issues between CCF and HDMI PHY config state, >> because the .set_rate() callback is not invoked when clock rate remains >> constant. This may also happen when the PHY PLL has been pre-programmed >> by an external entity, e.g. the bootloader, which is actually a >> regression introduced by the recent FRL patches. > > Don't mention 'patches' in description. Once the patch gets merged, it becomes a > commit. If needed, reference the offending commit(s) directly. Ack. I will reword if there is a need for v6. >> >> Introduce a pll_config_dirty flag to keep track of uncommitted PHY >> config changes and use it in clk_ops.determine_rate() to invalidate the >> current clock rate (as known by CCF) and, consequently, ensure those >> changes are programmed into hardware via clk_ops.set_rate(). >> >> Moreover, proceed with a similar fix in phy_ops.power_on() callback, to >> handle the scenario where the CCF API is not used due to operating in >> FRL mode, while the clock is still in a prepared state and thus >> preventing rk_hdptx_phy_consumer_get() to apply the updated PHY >> configuration. >> >> Fixes: de5dba833118 ("phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support") >> Fixes: 9d0ec51d7c22 ("phy: rockchip: samsung-hdptx: Add high color depth management") >> Tested-by: Thomas Niederprüm >> Tested-by: Simon Wright >> Tested-by: Diederik de Haas # NanoPC-T6 LTS >> Reviewed-by: Andy Yan >> Signed-off-by: Cristian Ciocaltea > > Reviewed-by: Manivannan Sadhasivam Thanks, Cristian