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Thu, 05 Nov 2026 13:44:50 -0800 (PST) Received: from [192.168.1.9] ([106.222.231.155]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b245c2de58sm17925920c88.12.2026.11.05.13.44.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Nov 2026 13:44:49 -0800 (PST) Message-ID: Date: Fri, 6 Nov 2026 03:14:42 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 06/15] drm/msm/a8xx: Allow nonctx reglist to include GMU regs To: Rob Clark , dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Bhaskar Reddy Valluru , Nico Angelo Dela Cruz , Konrad Dybcio , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , open list References: <20261105203057.66520-1-robin.clark@oss.qualcomm.com> <20261105203057.66520-7-robin.clark@oss.qualcomm.com> Content-Language: en-US From: Akhil P Oommen In-Reply-To: <20261105203057.66520-7-robin.clark@oss.qualcomm.com> Content-Type: text/plain; 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But from dt perspective it is > it's own device with a separate io space. So we need to detect this and > direct writes to the correct place. > > Acked-by: Konrad Dybcio > Tested-by: Alexander Koskovich # Milos (Nothing Phone 3a) > Signed-off-by: Rob Clark > --- > drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > index a29f8149493c..59898b49a201 100644 > --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > @@ -373,6 +373,7 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu) > static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) > { > struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > + struct a6xx_gmu *gmu = &to_a6xx_gpu(adreno_gpu)->gmu; > const struct a6xx_info *info = adreno_gpu->info->a6xx; > const struct adreno_reglist_pipe *regs = info->nonctxt_reglist; > unsigned int pipe_id, i; > @@ -392,7 +393,11 @@ static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) > if (regs[i].offset == REG_A8XX_RB_GC_GMEM_PROTECT) > *gmem_protect = regs[i].value; > > - gpu_write(gpu, regs[i].offset, regs[i].value); > + if ((regs[i].offset << 2) >= gmu->mmio_offset) { > + gmu_write(gmu, regs[i].offset, regs[i].value); > + } else { > + gpu_write(gpu, regs[i].offset, regs[i].value); > + } Any thoughts on a common IO accessor that can handle both gpu and gmu registers? We had issues in the past where GMU offset was used with gpu_write(). We can avoid those confusions with a unified routine for both GPU and GMU registers. Anyway, for this patch: Reviewed-by: Akhil P Oommen -Akhil > } > > a8xx_aperture_release(gpu, flags);